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w wm8974 mono codec with speaker driver wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ production data, rev 4.2 march 2007 copyright ? 2007 wolfson microelectronics plc description the wm8974 is a low power, high quality mono codec designed for portable applications such as digital still camera or digital voice recorder. the device integrates support for a differential or single ended mic, and includes drivers for speakers or headphone, and mono line output. external component requirements are reduced as no separate microphone or headphone amplifiers are required. advanced sigma delta converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 to 48ks/s. additional digital filtering options are available in the adc path, to cater for application filtering such as ?wind noise reduction?, plus an advanced mixed signal alc function with noise gate is provided. the digital audio interface supports a-law and -law companding. an on-chip pll is provided to generate the required master clock from an external reference clock. the pll clock can also be output if required elsewhere in the system. the wm8974 operates at supply voltages from 2.5 to 3.6v, although the digital supplies can operate at voltages down to 1.71v to save power. the speaker and mono outputs use a separate supply of up to 5v which enables increased output power if required. different sections of the chip can also be powered down under software control by way of the selectable two or three wire control interface. wm8974 is supplied in a very small 4x4mm qfn package, offering high levels of functionality in minimum board area, with high thermal performance. features ? mono codec: ? audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48khz ? dac snr 98db, thd -84db (?a?-weighted @ 8 ? 48ks/s) ? adc snr 94db, thd -83db (?a?-weighted @ 8 ? 48ks/s) ? on-chip headphone/speaker driver with ?cap-less? connect - 40mw output power into 16 ? / 3.3v spkvdd - btl speaker drive 0.9w into 8 ? / 5v spkvdd ? additional mono line output ? multiple analog or ?aux? inputs, plus analog bypass path ? mic preamps: ? differential or single end microphone interface - programmable preamp gain - psuedo differential inputs with common mode rejection - programmable alc / noise gate in adc path ? low-noise bias supplied for electret microphones other features ? 5 band eq (record or playback path) ? digital playback limiter ? programmable adc high pass filter (wind noise reduction) ? programmable adc notch filter ? on-chip pll ? low power, low voltage - 2.5v to 3.6v (digital: 1.71v to 3.6v) - power consumption <10ma all-on 48ks/s mode ? 4x4x0.9mm 24 lead qfn package applications ? digital still camera audio codec ? wireless voip and other communication device handsets / headsets ? portable audio recorder ? general purpose low power audio codec
wm8974 production data w pd rev 4.2 march 2007 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................3 ordering information ..................................................................................3 pin description ................................................................................................4 absolute maximum ratings.........................................................................5 recommended operating conditions .....................................................5 electrical characteristics ......................................................................6 terminology ............................................................................................................ 8 signal timing requirements .......................................................................9 system clock timing ............................................................................................. 9 audio interface timing ? master mode .......................................................... 9 audio interface timing ? slave mode............................................................ 10 control interface timing ? 3-wire mode .................................................... 11 control interface timing ? 2-wire mode .................................................... 12 device description .......................................................................................13 introduction ......................................................................................................... 13 input signal path ................................................................................................. 14 analogue to digital converter (adc).......................................................... 19 input limiter / automatic level control (alc) .......................................... 23 output signal path ............................................................................................. 35 analogue outputs............................................................................................... 42 output switch ...................................................................................................... 47 digital audio interfaces................................................................................... 49 audio sample rates ............................................................................................. 54 master clock and phase locked loop (pll) ............................................... 55 general purpose input/output...................................................................... 57 control interface.............................................................................................. 57 resetting the chip........................................................................................58 power supplies .................................................................................................... 58 power management ............................................................................................ 63 register map...................................................................................................65 register bits by address ................................................................................. 66 digital filter characteristics ...............................................................77 terminology .......................................................................................................... 77 dac filter responses......................................................................................... 78 adc filter responses......................................................................................... 78 de-emphasis filter responses........................................................................ 79 highpass filter..................................................................................................... 80 5-band equaliser .................................................................................................. 81 applications information .........................................................................85 recommended external components .......................................................... 85 package diagram ..........................................................................................86 important notice ..........................................................................................87 address: .................................................................................................................. 87
production data wm8974 w pd rev 4.2 march 2007 3 pin configuration top view ordering information order code temperature range package moisture sensitivity level package body temperature wm8974gefl/v -25 c to +85 c 24-lead qfn (4x4x0.9mm) (pb-free) msl3 260 o c wm8974gefl/rv -25 c to +85 c 24-lead qfn (4x4x0.9mm) (pb-free, tape and reel) msl3 260 o c note: reel quantity = 3,500
wm8974 production data w pd rev 4.2 march 2007 4 pin description pin no name type description 1 micbias analogue output microphone bias 2 avdd supply analogue supply (feeds adc and dac) 3 agnd supply analogue ground (feeds adc and dac) 4 dcvdd supply digital core supply 5 dbvdd supply digital buffer (input/output) supply 6 dgnd supply digital ground 7 adcdat digital output adc digital audio data output 8 dacdat digital input dac digital audio data input 9 frame digital input / output dac and adc sample rate clock or frame synch 10 bclk digital input / output digital audio port clock 11 mclk digital input master clock input 12 csb/gpio digital input / output 3-wire mpu chip select or general purpose input/output pin. 13 sclk digital input 3-wire mpu clock input / 2-wire mpu clock input 14 sdin digital input / output 3-wire mpu data input / 2-wire mpu data input 15 mode digital input control interface mode selection pin. 16 monoout analogue output mono output 17 spkoutp analogue output speaker output positive 18 spkgnd supply speaker ground (feeds speaker and mono output amps only) 19 spkoutn analogue output speaker output negative 20 spkvdd supply speaker supply (feeds speaker and mono output amps only) 21 aux analogue input auxiliary analogue input 22 vmid reference decoupling for midrail reference voltage 23 micn analogue input microphone negative input 24 micp analogue input microphone positive input (common mode) note: it is recommended that the qfn ground paddle should be connected to analogue ground on the application pcb.
production data wm8974 w pd rev 4.2 march 2007 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max dbvdd, dcvdd, avdd supply voltages -0.3v +4.2 spkvdd supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v operating temperature range, t a -25 c +85 c storage temperature prior to soldering 30 c max / 85% rh max storage temperature after soldering -65 c +150 c notes 1. analogue and digital grounds must always be within 0.3v of each other. 2. all digital and analogue supplies are completely independent from each other. recommended operating conditions parameter symbol test conditions min typ max unit digital supply range (core) dcvdd 1.71 3.6 v digital supply range (buffer) dbvdd 1.71 3.6 v analogue supplies range avdd 2.5 3.6 v speaker supply spkvdd 2.5 5.5 v ground dgnd,agnd,spkgnd 0 v notes 1. when using pll, dcvdd must be 1.9v or higher. 2. avdd must be dcvdd. 3. dbvdd must be dcvdd. 4. in non-boosted mode, spkvdd must be avdd, if boosted spkvdd must be 1.5x avdd. 5. when using pll, dcvdd must be 1.9v.
wm8974 production data w pd rev 4.2 march 2007 6 electrical characteristics test conditions dcvdd = 1.8v, avdd = dbvdd = 3.3v, spkvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit microphone inputs (micn, micp) full-scale input signal level (note 1) ? note this changes with avdd v infs pgaboost = 0db inppgavol = 0db 1.0 0 vrms dbv mic pga equivalent input noise at 35.25db gain 150 uv input resistance r micin gain set to 35.25db 1.6 k ? input resistance r micin gain set to 0db 47 k ? input resistance r micin gain set to -12db 75 k ? input resistance r micip micp2inppga = 1 94 k ? input resistance r micip micp2inppga = 0 94 k ? input capacitance c micin 10 pf mic input programmable gain amplifier (pga) programmable gain -12 35.25 db programmable gain step size guaranteed monotonic 0.75 db mute attenuation 108 db selectable input gain boost (0/+20db) gain boost 0 20 db automatic level control (alc)/limiter ? adc only target record level -28.5 -6 db programmable gain -12 35.25 db programmable gain step size guaranteed monotonic 0.75 db gain hold time (note 2) t hold mclk=12.288mhz (note 4) 0, 2.67, 5.33, 10.67, ? , 43691 (time doubles with each step) ms alcmode=0 (alc), mclk=12.288mhz (note 4) 3.3, 6.6, 13.1, ? , 3360 (time doubles with each step) gain ramp-up (decay) time (note 3) t dcy alcmode=1 (limiter), mclk=12.288mhz (note 4) 0.73, 1.45, 2.91, ? , 744 (time doubles with each step) ms alcmode=0 (alc), mclk=12.288mhz (note 4) 0.83, 1.66, 3.33, ? , 852 (time doubles with each step) gain ramp-down (attack) time (note 3) t atk alcmode=1 (limiter), mclk=12.288mhz (note 4) 0.18, 0.36, 0.73, ? , 186 (time doubles with each step) ms analogue to digital converter (adc) signal to noise ratio (note 5) snr a-weighted, 0db pga gain 85 94 db total harmonic distortion (note 6) thd -1dbfs input, 0db pga gain -75 -83 db auxilliary analogue input (aux) full-scale input signal level (0db) ? note this changes with avdd v infs 1.0 0 vrms dbv input resistance r auxin auxmode=0 20 k ? input capacitance c auxin 10 pf
production data wm8974 w pd rev 4.2 march 2007 7 test conditions dcvdd = 1.8v, avdd = dbvdd = 3.3v, spkvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit digital to analogue converter (dac) to mono output (all data measured with 10k ? / 50pf load) signal to noise ratio (note 5) snr a-weighted 90 98 db total harmonic distortion + noise (note 6) thd+n r l = 10 k ? full-scale signal -84 db monoboost=0 avdd/3.3 0db full scale output voltage (note 9 ) monoboost=1 1.5x (avdd/3.3) v rms speaker output pga programmable gain -57 6 db programmable gain step size guaranteed monotonic 1 db btl speaker output (spkoutp, spkoutn with 8 ? bridge tied load) output power p o output power is very closely correlated with thd; see below p o =180mw, r l = 8 ? , spkvdd=3.3v 0.03 -70 % db p o =400mw, r l = 8 ? , spkvdd=3.3v 5.0 -26 % db p o =360mw, r l = 8 ? , spkvdd=5v 0.02 -75 % db total harmonic distortion + noise (note 6) thd+n p o =800mw, r l = 8 ? , spkvdd=5v 0.06 -65 % db spkvdd=3.3v, r l = 8 ? 90 101 db signal to noise ratio snr spkvdd=5v, r l = 8 ? 102 db power supply rejection ratio 50 db ?headphone? output (spkoutp, spkoutn with resistive load to ground) signal to noise ratio snr 100 db total harmonic distortion + noise (note 6) thd+n po=20mw, r l = 16 ? , spkvdd=3.3v 0.02 -74 % db po=20mw, r l = 32 ? , spkvdd=3.3v 0.017 - 75 % db microphone bias bias voltage (mbvsel=0) v micbias 0.9*avdd v bias voltage (mbvsel=1) v micbias 0.65*avdd v bias current source i micbias 3 ma output noise voltage vn 1k to 20khz 15 nv/ hz digital input / output input high level v ih 0.7 dvdd v input low level v il 0.3 dvdd v output high level v oh i ol =1ma 0.9 dvdd v output low level v ol i oh -1ma 0.1xdvdd v
wm8974 production data w pd rev 4.2 march 2007 8 terminology 1. micn input only in single ended microphone configuration. maximum input signal to micp without distortion is -3dbv. 2. hold time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. it does not apply to ramping down the gain when the signal is too loud, which happens without a delay. 3. ramp-up and ramp-down times are defined as the time it takes for the pga to change it?s gain by 6db. 4. all hold, ramp-up and ramp-down times scale proportionally with mclk 5. signal-to-noise ratio (db) ? snr is a measure of the difference in level between the full scale output and the output with no signal applied. (no auto-zero or automute function is employed in achieving these results). 6. thd+n (db) ? thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 7. the maximum output voltage can be limited by the speaker power supply. if monoboost=1 then spkvdd s hould be 1.5xavdd or higher to prevent clipping taking place in the output stage.
production data wm8974 w pd rev 4.2 march 2007 9 signal timing requirements system clock timing mclk t mclkl t mclkh t mclky figure 1 system clock timing requirements test conditions dcvdd=1.8v, dbvdd=avdd=spkvdd=3.3v, dgnd=agnd=spkgnd=0v, t a = +25 o c parameter symbol conditions min typ max unit system clock timing information mclk=sysclk (=256fs) 81.38 ns mclk cycle time t mclky mclk input to pll note 1 20 ns mclk duty cycle t mclkds 60:40 40:60 note 1: pll pre-scaling and pll n and k values should be set appropriately so that sysclk is no greater t han 12.288mhz. audio interface timing ? master mode figure 2 digital audio data timing ? master mode (see control interface)
wm8974 production data w pd rev 4.2 march 2007 10 test conditions dcvdd=1.8v, dbvdd=avdd=spkvdd=3.3v, dgnd=agnd=spkgnd=0v, t a =+25 o c, master mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information frame propagation delay from bclk falling edge t dl 10 ns adcdat propagation delay from bclk falling edge t dda 10 ns dacdat setup time to bclk rising edge t dst 10 ns dacdat hold time from bclk rising edge t dht 10 ns note: bclk period should always be greater than mclk period. audio interface timing ? slave mode figure 3 digital audio data timing ? slave mode test conditions dcvdd=1.8v, dbvdd=avdd=spkvdd=3.3v, dgnd=agnd=spkgnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk= 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 160 ns bclk pulse width high t bch 64 ns bclk pulse width low t bcl 64 ns frame set-up time to bclk rising edge t lrsu 10 ns frame hold time from bclk rising edge t lrh 10 ns dacdat hold time from bclk rising edge t dh 10 ns dacdat set-up time to bclk rising edge t ds 10 ns adcdat propagation delay from bclk falling edge t dd 20 ns
production data wm8974 w pd rev 4.2 march 2007 11 control interface timing ? 3-wire mode figure 4 control interface timing ? 3-wire serial control mode test conditions dcvdd = 1.8v, dbvdd = avdd = spkvdd = 3.3v, dgnd = agnd = spkgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb rising edge t scs 80 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sclk to sdin hold time t dho 40 ns csb pulse width low t csl 40 ns csb pulse width high t csh 40 ns csb rising to sclk rising t css 40 ns pulse width of spikes that will be suppressed t ps 0 5 ns
wm8974 production data w pd rev 4.2 march 2007 12 control interface timing ? 2-wire mode sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 5 control interface timing ? 2-wire serial control mode test conditions dcvdd=1.8v, dbvdd=avdd=spkvdd=3.3v, dgnd=agnd=spkgnd=0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 0 526 khz sclk low pulse-width t 1 1.3 us sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
production data wm8974 w pd rev 4.2 march 2007 13 device description introduction the wm8974 is a low power audio codec combining a high quality mono audio dac and adc, with flexible line and microphone input and output processing. applications for this device include digital still cameras with mono audio, record and playback capability, voice recorders, wireless voip headsets and games console accessories. features the chip offers great flexibility in use, and so can support many different modes of operation as follows: microphone inputs two microphone inputs are provided, allowing for either a differential microphone input or a single ended microphone to be connected. these inputs have a user programmable gain range of -12db to +35.25db using internal resistors. after the input pga stage comes a boost stage which can add a further 20db of gain. a microphone bias is output from the chip which can be used to bias the microphones. the signal routing can be configured to allow manual adjustment of mic levels, or to allow the alc loop to control the level of mic signal that is transmitted. total gain through the microphone paths of up to +55.25db can be selected. pga and alc operation a programmable gain amplifier is provided in the input path to the adc. this may be used manually or in conjunction with a mixed analogue/digital automatic level control (alc) which keeps the recording volume constant. aux input the device includes a mono input, aux, that can be used as an input for warning tones (beep) etc. the output from this circuit can be summed into the mono output and/or the speaker output paths, so allowing for mixing of audio with ?backing music? etc as required. this path can also be summed into the input in a flexible fashion, either to the input pga as a second microphone input or as a line input. the configuration of this circuit, with integrated on-chip resistors allows several analogue signals to be summed into the single aux input if required. adc the mono adc uses a multi-bit high-order oversampling architecture to deliver optimum performance with low power consumption. various sample rates are supported, from the 8ks/s rate typically used in voice dictation, up to the 48ks/s rate used in high quality audio applications. hi-fi dac the hi-fi dac provides high quality audio playback suitable for all portable mono audio type applications. digital filtering advanced sigma delta converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8ks/s to 48ks/s. application specific digital filters are also available which help to reduce the effect of specific noise sources such as ?wind noise?. the filters include a programmable adc high pass filter, a programmable adc notch filter and a 5-band equaliser that can be applied to either the adc or the dac path in order to improve the overall audio sound from the device. output mixing and volume adjust flexible mixing is provided on the outputs of the device; a mixer is provided for the speaker outputs, and an additional mono summer for the mono output. these mixers allow the output of the dac, the output of the adc volume control and the auxilliary input to be combined. the output volume can be adjusted using the integrated digital volume control and there is additional analogue gain adjustment capability on the speaker output. audio interfaces the wm8974 has a standard audio interface, to support the transmission of audio data to and from the chip. this interface is a 4 wire standard audio interface which supports a number of audio data formats including i 2 s, dsp mode, msb-first, left justified and msb-first, right justified, and can operate in master or slave modes.
wm8974 production data w pd rev 4.2 march 2007 14 control interfaces to allow full software control over all its features, the wm8974 offers a choice of 2 or 3 wire mpu control interface. it is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and dsps. the selection between 2-wire mode and 3-wire mode is determined by the state of the mode pin. if mode is high then 3-wire control mode is selected, if mode is low then 2-wire control mode is selected. in 2 wire mode, only slave operation is supported, and the address of the device is fixed as 0011010. clocking schemes wm8974 offers the normal audio dac clocking scheme operation, where 256fs mclk is provided to the dac/adc. however, a pll is also included which may be used to generate the internal master clock frequency in the event that this is not available from the system controller. this pll uses an input clock, typically the 12mhz usb or ilink clock, to generate high quality audio clocks. if this pll is not required for generation of these clo cks, it can be reconfigured to generate alternative clocks which may then be output on the csb/gpio pin and used elsewhere in the system. power control the design of the wm8974 has given much attention to power consumption without compromising performance. it operates at low supply voltages, and includes the facility to power off any unused parts of the circuitry under software control, includes standby and power off modes. input signal path the wm8974 has 3 flexible analogue inputs: two microphone inputs, and an auxiliary input. these inputs can be used in a variety of ways. the input signal path before the adc has a flexible pga block which then feeds into a gain boost/mixer stage. microphone inputs the wm8974 can accommodate a variety of microphone configurations including single ended and differential inputs. the inputs through the micn, micp and optionally aux pins are amplified through the input pga as shown in figure 6 . a pseudo differential input is the preferential configuration where the positive terminal of the input pga is connected to the micp input pin by setting micp2inppga=1. the microphone ground should then be connected to micn (when micn2inppga=1) or optionally to aux (when aux2inppga=1) input pins. alternatively a single ended microphone can be connected to the micn input with micn2inppga set to 1. the non-inverting terminal of the input pga should be connected internally to vmid by setting micp2inppga to 0. in differential mode the larger signal should be input to micp and the smaller (e.g. noisy ground connection) should be input to micn.
production data wm8974 w pd rev 4.2 march 2007 15 figure 6 microphone input pga circuit (switch positions shown are for differential mic input) register address bit label default description 0 micp2inppga 1 connect input pga amplifier positive terminal to micp or vmid. 0 = input pga amplifier positive terminal connected to vmid 1 = input pga amplifier positive terminal connected to micp through variable resistor string 1 micn2inppga 1 connect micn to input pga negative terminal. 0=micn not connected to input pga 1=micn connected to input pga amplifier negative terminal. r44 input control 2 aux2inppga 0 select aux amplifier output as input pga signal source. 0=aux not connected to input pga 1=aux connected to input pga amplifier negative terminal. the input pga is enabled by the ippgaen register bit. register address bit label default description r2 power management 2 2 inppgaen 0 input microphone pga enable 0 = disabled 1 = enabled
wm8974 production data w pd rev 4.2 march 2007 16 input pga volume control the input microphone pga has a gain range from -12db to +35.25db in 0.75db steps. the gain from the micn input to the pga output and from the aux amplifier to the pga output are always common and controlled by the register bits inppgavol[5:0]. these register bits also affect the micp pin when micp2inppga=1. when the automatic level control (alc) is enabled the input pga gain is then controlled automatically and the inppgavol bits should not be used. register address bit label default description 5:0 inppgavol 010000 input pga volume 000000 = -12db 000001 = -11.25db . 010000 = 0db . 111111 = 35.25db 6 inppgamute 0 mute control for input pga: 0=input pga not muted, normal operation 1=input pga muted (and disconnected from the following input boost stage). r45 input pga volume control 7 inppgazc 0 input pga zero cross enable: 0=update gain when gain register changes 1=update gain on 1 st zero cross after gain register write. r32 alc control 1 8 alcsel 0 alc function select: 0=alc off (pga gain set by inppgavol register bits) 1=alc on (alc controls pga gain) table 1 input pga volume control auxilliary input an auxilliary input circuit (figure 7) is provided which consists of an amplifier which can be configured either as an inverting buffer for a single input signal or as a mixer/summer for multiple inputs with the use of external resistors. the circuit is enabled by the register bit auxen. figure 7 auxiliary input circuit the auxmode register bit controls the auxiliary input mode of operation: in buffer mode (auxmode=0) the switch labelled auxsw in figure 7 is open and the signal at the aux pin will be buffered and inverted through the aux circuit using only the internal components.
production data wm8974 w pd rev 4.2 march 2007 17 in mixer mode (auxmode=1) the on-chip input resistor is bypassed, this allows the user to sum in multiple inputs with the use of external resistors. when used in this mode there will be gain variations through this path from part to part due to the variation of the internal 20k ? resistors relative to the higher tolerance external resistors. register address bit label default description r1 power management 1 6 auxen 0 auxiliary input buffer enable 0 = off 1 = on r44 input control 3 auxmode 0 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed) table 2 auxiliary input buffer control input boost the input boost circuit has 3 selectable inputs: the input microphone pga output, the aux amplifier output and the micp input pin (when not using a differential microphone configuration). these three inputs can be mixed together and have individual gain boost/adjust as shown in figure 8. figure 8 input boost stage the input pga path can have a +20db boost (pgaboost=1) a 0db pass through (pgaboost=0) or be completely isolated from the input boost circuit (inppgamute=1). register address bit label defaul t description r45 input pga gain control 6 inppgamute 0 mute control for input pga: 0=input pga not muted, normal operation 1=input pga muted (and disconnected from the following input boost stage). r47 input boost control 8 pgaboost 0 0 = pga output has +0db gain through input boost stage. 1 = pga output has +20db gain through input boost stage. table 3 input boost stage control the auxiliary amplifier path to the boost stage is controlled by the aux2boostvol[2:0] register bits. when aux2boostvol=000 this path is completely disconnected from the boost stage. settings 001 through to 111 control the gain in 3db steps from -12db to +6db.
wm8974 production data w pd rev 4.2 march 2007 18 the micp path to the boost stage is controlled by the micp2boostvol[2:0] register bits. when micp2boostvol=000 this input pin is completely disconnected from the boost stage. settings 001 through to 111 control the gain in 3db steps from -12db to +6db. register address bit label defaul t description 2:0 aux2boostvol 000 controls the auxiliary amplifier to the input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage r47 input boost control 6:4 micp2boostvol 000 controls the micp pin to the input boost stage (nb, when using this path set micp2inppga=0): 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage table 4 input boost stage control the boost stage is enabled under control of the boosten register bit. register address bit label default description r2 power management 2 4 boosten 0 input boost enable 0 = boost stage off 1 = boost stage on table 5 input boost enable control microphone biasing circuit the micbias output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. refer to the applications information section for recommended external components. the micbias voltage can be altered via the mbvsel register bit. w hen m bvsel=0, micbias=0.9*avdd and when m bvsel=1, micbias=0.65*avdd. the output can be enabled or disabled using the micben control bit. register address bit label default description r1 power management 1 4 micben 0 microphone bias enable 0 = off (high impedance output) 1 = on table 6 microphone bias enable register address bit label default description r44 input control 8 mbvsel 0 microphone bias voltage control 0 = 0.9 * avdd 1 = 0.65 * avdd table 7 microphone bias voltage control the internal micbias circuitry is shown in figure 9. note that the maximum source current capability for micbias is 3ma. the external biasing resistors therefore must be large enough to limit the micbias current to 3ma.
production data wm8974 w pd rev 4.2 march 2007 19 figure 9 microphone bias schematic analogue to digital converter (adc) the wm8974 uses a multi-bit, oversampled sigma-delta adc channel. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full scale input level is proportional to avdd. with a 3.3v supply voltage, the full scale level is 1.0v rms . any voltage greater than full scale may overload the adc and cause distortion. adc digital filters the adc filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the adc to the correct sampling frequency to be output on the digital audio interface. the digital filter path is illustrated in . figure 10 adc digital filter path the adc is enabled by the adcen register bit. register address bit label default description r2 power management 2 0 adcen 0 0 = adc disabled 1 = adc enabled table 8 adc enable agnd mbvsel=0 micbias = 1.8 x vmid = 0.9 x avdd vmid internal resistor internal resistor mb mbvsel=1 micbias = 1.3 x vmid = 0.65 x avdd
wm8974 production data w pd rev 4.2 march 2007 20 the polarity of the output signal can also be changed under software control using the adcpol register bit. the oversampling rate of the adc can be adjusted using the adcosr register bit. with adcosr=0 the oversample rate is 64x which gives lowest power operation and when adcosr=1 the oversample rate is 128x which gives best performance. register address bit label default description 3 adcosr 0 adc oversample rate select: 0=64x (lower power) 1=128x (best performance) r14 adc control 0 adcpol 0 0=normal 1=inverted table 9 adc oversample rate select selectable high pass filter a selectable high pass filter is provided. to disable this filter set hpfen=0. the filter has two modes controlled by hpfapp. in audio mode (hpfapp=0) the filter is first order, with a cut-off frequency of 3.7hz. in application mode (hpfapp=1) the filter is second order, with a cut-off frequency selectable via the hpfcut register. the cut-off frequencies when hpf app=1 are shown in table 11. register address bit label default description 8 hpfen 1 high pass filter enable 0=disabled 1=enabled 7 hpfapp 0 select audio mode or application m ode 0=audio mode (1 st order, fc = ~3.7hz) 1=application mode (2 nd order, fc = hpfcut) r14 adc control 6:4 hpfcut 000 application mode cut-off frequency see table 11 for details. table 10 adc filter select fs (khz) sr=101/100 sr=011/010 sr=001/000 hpfcut 8 11.025 12 16 22.05 24 32 44.1 48 000 82 113 122 82 113 122 82 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 156 131 180 156 131 180 156 011 163 225 245 163 225 245 163 225 245 100 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 327 450 490 111 408 563 612 408 563 612 408 563 612 table 11 high pass filter cut-off frequencies (hpfapp=1) note that the high pass filter values (when hpfapp=1) work on the basis that the sr register bits are set correctly for the actual sample rate as shown in table 11.
production data wm8974 w pd rev 4.2 march 2007 21 programmable notch filter a programmable notch filter is provided. this filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits nfa0[13:0] and nfa1[13:0]. because these coefficient values require four register writes to setup there is an nfu (notch filter update) flag which should be set only when all four registers are setup. register address bit label default description 6:0 nfa0[13:7] 0 notch filter a0 coefficient, bits [13:7] 7 nfen 0 notch filter enable: 0=disabled 1=enabled r27 notch filter 1 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. 6:0 nfa0[6:0] 0 notch filter a0 coefficient, bits [6:0] r28 notch filter 2 8 nfu] 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. 6:0 nfa1[13:7] 0 notch filter a1 coefficient, bits [13:7] r29 notch filter 3 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. 6:0 nfa1[6:0] 0 notch filter a1 coefficient, bits [6:0] r30 notch filter 4 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. table 12 notch filter function the coefficients are calculated as follows: ) 2 / tan( 1 ) 2 / tan( 1 0 b b w w a + ? = ) cos( ) 1 ( 0 0 1 w a a + ? = where: s c f f w / 2 0 = s b b f f w / 2 = f c = centre frequency in hz, f b = -3db bandwidth in hz, f s = sample frequency in hz the actual register values can be determined from the coefficients as follows: nfa0 = -a0 x 2 13 nfa1 = -a1 x 2 12
wm8974 production data w pd rev 4.2 march 2007 22 digital adc volume control the output of the adcs can be digitally attenuated over a range from ?127db to 0db in 0.5db steps. the gain for a given eight-bit code x is given by: gain = 0.5 x (x?255) db for 1 x 255, mute for x = 0 register address bit label default description r15 adc digital volume 7:0 adcvol [7:0] 11111111 ( 0db ) adc digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db table 13 adc volume
production data wm8974 w pd rev 4.2 march 2007 23 input limiter / automatic level control (alc) the wm8974 has an automatic pga gain control circuit, which can function as an input peak limiter or as an automatic level control (alc). the automatic level control (alc) provides continuous adjustment of the input pga in response to the amplitude of the input signal. a digital peak detector monitors the input signal amplitude and compares it to a register defined threshold level (alclvl). if the signal is below the threshold, the alc will increase the gain of the pga at a rate set by alcdcy. if the signal is above the threshold, the alc will reduce the gain of the pga at a rate set by alcatk. the alc has two modes selected by the alcmode register: normal mode and peak limiter mode. the alc/limiter function is enabled by setting the register bit r32[8] alcsel. register address bit label default description 2:0 alcmin [2:0] 000 (-12db) set minimum gain of pga 000 = -12db 001 = -6db 010 = 0db 011 = +6db 100 = +12db 101 = +18db 110 = +24db 111 = +30db 5:3 alcmax [2:0] 111 (+35.25db) set maximum gain of pga 111 = +35.25db 110 = +29.25db 101 = +23.25db 100 = +17.25db 011 = +11.25db 010 = +5.25db 001 = -0.75db 000 = -6.75db r32 (20h) alc control 1 8 alcsel 0 alc function select 0 = alc disabled 1 = alc enabled r33 (21h) alc control 2 3:0 alclvl [3:0] 1011 (-12db) alc target ? sets signal level at adc input 1111 = -6dbfs 1110 = -7.5dbfs 1101 = -9dbfs 1100 = -10.5dbfs 1011 = -12dbfs 1010 = -13.5dbfs 1001 = -15dbfs 1000 = -16.5dbfs 0111 = -18dbfs 0110 = -19.5dbfs 0101 = -21dbfs 0100 = -22.5dbfs 0011 = -24dbfs 0010 = -25.5dbfs 0001 = -27dbfs 0000 = -28.5dbfs
wm8974 production data w pd rev 4.2 march 2007 24 register address bit label default description 8 alczc 0 (zero cross off) alc uses zero cross detection circuit. 0 = disabled (recommended) 1 = enabled 7:4 alchld [3:0] 0000 (0ms) alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s 1000 = 0.34s 1001 = 0.68s 1010 or higher = 1.36s 8 alcmode 0 determines the alc mode of operation: 0 = alc mode (normal operation) 1 = limiter mode. decay (gain ramp-up) time (alcmode ==0) per step per 6db 90% of range 0000 410us 3.38ms 23.6ms 0001 820us 6.56ms 47.2ms 0010 1.64ms 13.1ms 94.5ms ? (time doubles with every step) 0011 (26ms/6db) 1010 or higher 420ms 3.36s 24.2s decay (gain ramp-up) time (alcmode ==1) per step per 6db 90% of range 0000 90.8us 726us 5.23ms 0001 182us 1.45ms 10.5ms 0010 363us 2.91ms 20.9ms ? (time doubles with every step) 7:4 alcdcy [3:0] 0011 (5.8ms/6db) 1010 93ms 744ms 5.36s alc attack (gain ramp-down) time (alcmode == 0) per step per 6db 90% of range 0000 104us 832us 6ms 0001 208us 1.66ms 12ms 0010 416us 3.33ms 24ms ? (time doubles with every step) 0010 (3.3ms/6db) 1010 or higher 106ms 852ms 6.13s alc attack (gain ramp-down) time (alcmode == 1) per step per 6db 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363us 2.62ms 0010 90.8us 726us 5.23ms ? (time doubles with every step) r34 (22h) alc control 3 3:0 alcatk [3:0] 0010 (726us/6db) 1010 or higher 23.2ms 186ms 1.34s table 14 alc control registers
production data wm8974 w pd rev 4.2 march 2007 25 when the alc is disabled, the input pga remains at the last controlled value of the alc. an input gain update must be made by writing to the inppgavoll/r register bits. normal mode in normal mode, the alc will attempt to maintain a constant signal level by increasing or decreasing the gain of the pga. the following diagram shows an example of this. figure 11 alc normal mode operation
wm8974 production data w pd rev 4.2 march 2007 26 limiter mode in limiter mode, the alc will reduce peaks that go above the threshold level, but will not increase the pga gain beyond the starting level. the starting level is the pga gain setting when the alc is enabled in limiter mode. if the alc is started in limiter mode, this is the gain setting of the pga at start-up. if the alc is switched into limiter mode after running in alc mode, the starting gain will be the gain at switchover. the diagram below shows an example of limiter mode. figure 12 alc limiter mode operation attack and decay times the attack and decay times set the update times for the pga gain. the attack time is the time constant used when the gain is reducing. the decay time is the time constant used when the gain is increasing. in limiter mode, the time constants are faster than in alc mode. the time constants are shown below in terms of a single gain step, a change of 6db and a change of 90% of the pgas gain range. note that, these times will vary slightly depending on the sample rate used (specified by the sr register).
production data wm8974 w pd rev 4.2 march 2007 27 normal mode alcmode = 0 (normal mode) alcatk t atk t atk6db t atk90% 0000 104s 832s 6ms 0001 208s 1.66ms 12ms 0010 416s 3.33ms 24ms 0011 832s 6.66ms 48ms 0100 1.66ms 13.3ms 96ms 0101 3.33ms 26.6ms 192ms 0110 6.66ms 53.2ms 384ms 0111 13.3ms 106ms 767ms 1000 26.6ms 213.2ms 1.53s 1001 53.2ms 426ms 3.07s 1010 106ms 852ms 6.13s attack time (s) alcmode = 0 (normal mode) alcdcy t dcy t dcy6db t dcy90% 0000 410s 3.28ms 23.6ms 0001 820s 6.56ms 47.2ms 0010 1.64ms 13.1ms 94.5ms 0011 3.28ms 26.2ms 189ms 0100 6.56ms 52.5ms 378ms 0101 13.1ms 105ms 756ms 0110 26.2ms 210ms 1.51s 0111 52.5ms 420ms 3.02s 1000 105ms 840ms 6.05s 1001 210ms 1.68s 12.1s 1010 420ms 3.36s 24.2s decay time (s) table 15 alc normal mode (attack and decay times)
wm8974 production data w pd rev 4.2 march 2007 28 limiter mode alcmode = 1 (limiter mode) alcatk t atklim t atklim6db t atklim90% 0000 22.7s 182s 1.31ms 0001 45.4s 363s 2.62ms 0010 90.8s 726s 5.23ms 0011 182s 1.45ms 10.5ms 0100 363s 2.91ms 20.9ms 0101 726s 5.81ms 41.8ms 0110 1.45ms 11.6ms 83.7ms 0111 2.9ms 23.2ms 167ms 1000 5.81ms 46.5ms 335ms 1001 11.6ms 93ms 669ms 1010 23.2ms 186ms 1.34s attack time (s) alcmode = 1 (limiter mode) alcdcy t dcylim t dcylim6db t dcylim90% 0000 90.8s 726s 5.23ms 0001 182s 1.45ms 10.5ms 0010 363s 2.91ms 20.9ms 0011 726s 5.81ms 41.8ms 0100 1.45ms 11.6ms 83.7ms 0101 2.91ms 23.2ms 167ms 0110 5.81ms 46.5ms 335ms 0111 11.6ms 93ms 669ms 1000 23.2ms 186ms 1.34s 1001 46.5ms 372ms 2.68s 1010 93ms 744ms 5.36s attack time (s) table 16 alc limiter mode (attack and decay times)
production data wm8974 w pd rev 4.2 march 2007 29 minimum and maximum gain the alcmin and alcmax register bits set the minimum/maximum gain value that the pga can be set to whilst under the control of the alc. this has no effect on the pga when alc is not enabled. register address bit label default description 5:3 alcmax 111 set maximum gain of pga r32 alc control 1 2:0 alcmin 000 set minimum gain of pga table 17 alc max/min gain in normal mode, alcmax sets the maximum boost which can be applied to the signal. in limiter mode, alcmax will normally have no effect (assuming the starting gain value is less than the maximum gain specified by alcmax) because the maximum gain is set at the starting gain level. alcmin sets the minimum gain value which can be applied to the signal. figure 13 alc min/max gain alcmax maximum gain (db) 111 35.25 110 29.25 101 23.25 100 17.25 011 11.25 010 5.25 001 -0.75 000 -6.75 table 18 alc max gain values
wm8974 production data w pd rev 4.2 march 2007 30 alcmin minimum gain (db) 000 -12 001 -6 010 0 011 6 100 12 101 18 110 24 111 30 table 19 alc min gain values note that if the alc gain setting strays outside the alc operating range, either by starting the alc outside of the range or changing the alcmax or alcmin settings during operation, the alc will immediately adjust the gain to return to the alc operating range. it is recommended that the alc starting gain is set between the alcmax and alcmin limits. alc hold time (normal mode only) in normal mode, the alc has an adjustable hold time which sets a time delay before the alc begins its decay phase (gain increasing). the hold time is set by the alchld register. register address bit label default description r33 alc control 2 7:4 alchld 0000 alc hold time before gain is increased. table 20 alc hold time if the hold time is exceeded this indicates that the signal has reached a new average level and the alc will increase the gain to adjust for that new average level. if the signal goes above the threshold during the hold period, the hold phase is abandoned and the alc returns to normal operation.
production data wm8974 w pd rev 4.2 march 2007 31 figure 14 alclvl
wm8974 production data w pd rev 4.2 march 2007 32 figure 15 alc hold time alchld t hold (s) 0000 0 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 85.4ms 0111 171ms 1000 342ms 1001 684ms 1010 1.37s table 21 alc hold time values
production data wm8974 w pd rev 4.2 march 2007 33 peak limiter to prevent clipping when a large signal occurs just after a period of quiet, the alc circuit includes a limiter function. if the adc input signal exceeds 87.5% of full scale (?1.16db), the pga gain is ramped down at the maximum attack rate (as when alcatk = 0000), until the signal level falls below 87.5% of full scale. this function is automatically enabled whenever the alc is enabled. note: if alcatk = 0000, then the limiter makes no difference to the operation of the alc. it is designed to prevent clipping when long attack times are used. noise gate (normal mode only) when the signal is very quiet and consists mainly of noise, the alc function may cause ?noise pumping?, i.e. loud hissing noise during silence periods. the wm8974 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, ngth. the noise gate cuts in when: signal level at adc [dbfs] < ngth [dbfs] + pga gain [db] + mic boost gain [db] this is equivalent to: signal level at input pin [dbfs] < ngth [dbfs] the pga gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). the table below summarises the noise gate control register. the ngth control bits set the noise gate threshold with respect to the adc full-scale range. the threshold is adjusted in 6db steps. levels at the extremes of the range may cause inappropriate operation, so care should be taken with set?up of the function. the noise gate only operates in conjunction with the alc and cannot be used in limiter mode. register address bit label default description 2:0 ngth 000 noise gate threshold: 000 = -39db 001 = -45db 010 = -51db 011 = -57db 100 = -63db 101 = -69db 110 = -75db 111 = -81db r35 (23h) alc noise gate control 3 ngaten 0 noise gate function enable 1 = enable 0 = disable table 22 alc noise gate control the diagrams below show the response of the system to the same signal with and without noise gate.
wm8974 production data w pd rev 4.2 march 2007 34 figure 16 alc operation above noise gate threshold
production data wm8974 w pd rev 4.2 march 2007 35 figure 17 noise gate operation output signal path the wm8974 output signal paths consist of digital application filters, up-sampling filters, a hi-fi dac, analogue mixers, speaker and mono output drivers. the digital filters and dac are enabled by bit dacen. the mixers and output drivers can be separately enabled by individual control bits (see analogue outputs). thus it is possible to utilise the analogue mixing and amplification provided by the wm8974, irrespective of whether the dacs are running or not. the wm8974 dac receives digital input data on the dacdat pin. the digital filter block processes the data to provide the following functions: ? digital volume control ? graphic equaliser ? a digital peak limiter. ? sigma-delta modulation the high performance sigma-delta audio dac converts the digital data into an analogue signal. figure 18 dac digital filter path
wm8974 production data w pd rev 4.2 march 2007 36 the analogue output from the dac can then be mixed with the aux analogue input and the adc analogue input. the mix is fed to the output drivers, spkoutp/n, and monoout. monoout: can drive a 16 ? or 32 ? headphone or line output or can be a buffered version of vmid (when monomute=1). spkoutp/n: can drive a 16 ? or 32 ? stereo headphone or stereo line output, or an 8 ? btl mono speaker. digital hi-fi dac volume control the signal volume from each hi-fi dac can be controlled digitally. the gain and attenuation range is ?127db to 0db in 0.5db steps. the level of attenuation for an eight-bit code x is given by: 0.5 (x-255) db for 1 x 255; mute for x = 0 register address bit label default description r11 dac digital volume 7:0 dacvol [7:0] 11111111 ( 0db ) dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db table 23 dac volume hi-fi digital to analogue converter (dac) after passing through the graphic equaliser filters, digital ?de-emphasis? can be applied to the audio data if necessary (e.g. when the data comes from a cd with pre-emphasis used in the recording). de-emphasis filtering is available for sample rates of 48khz, 44.1khz and 32khz. register address bit label default description r10 dac control 5:4 deemph 00 de-emphasis control 00 = no de-emphasis 01 = 32khz sample rate 10 = 44.1khz sample rate 11 = 48khz sample rate table 24 de-emphasis the dac is enabled by the dacen register bit. register address bit label default description r3 power management 3 0 dacen 0 dac enable 0 = dac disabled 1 = dac enabled table 25 dac enable the wm8974 also has a soft mute function, which gradually attenuates the volume of the digital signal to zero. when removed, the gain will ramp back up to the digital gain setting. this function is enabled by default. to play back an audio signal, it must first be disabled by setting the dacmu bit to zero. register address bit label default description r10 dac control 6 dacmu 0 dac soft mute enable 0 = dacmu disabled 1 = dacmu enabled table 26 dac control register
production data wm8974 w pd rev 4.2 march 2007 37 the digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. the bitstream data enters a multi-bit, sigma-delta dac, which converts it to a high quality analogue audio signal. the multi-bit dac architecture reduces high frequency noise and sensitivity to clock jitter. the dac output defaults to non-inverted. setting dacpol will invert the dac output phase. automute the dac has an automute function which applies an analogue mute when 1024 consecutive zeros are detected. the mute is release as soon as a non-zero sample is detected. automute can be disabled using the amute control bit. register address bit label default description r10 dac control 2 amute 0 dac auto mute enable 0 = auto mute disabled 1 = auto mute enabled table 27 dac auto mute control register dac output limiter the wm8974 has a digital output limiter function. the operation of this is shown in figure 19. in this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic. figure 19 dac digital limiter operation the limiter has a programmable upper threshold which is close to 0db. referring to table 28, in normal operation (limboost=000 => limit only) signals below this threshold are unaffected by the limiter. signals above the upper threshold are attenuated at a specific attack rate (set by the limatk register bits) until the signal falls below the threshold. the limiter also has a lower threshold 1db below the upper threshold. when the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by limdcy register bits) until a gain of 0db is reached. both threshold levels are controlled by the limlvl register bits. the upper threshold is 0.5db above the value programmed by limlvl and the lower threshold is 0.5db below the limlvl value.
wm8974 production data w pd rev 4.2 march 2007 38 volume boost the limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. this operates as an alc function with limited boost capability. the volume boost is from 0db to +12db in 1db steps, controlled by the limboost register bits. the output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.
production data wm8974 w pd rev 4.2 march 2007 39 register address bit label default description 3:0 limatk 0010 limiter attack time (per 6db gain change) for 44.1khz sampling. note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms 7:4 limdcy 0011 limiter decay time (per 6db gain change) for 44.1khz sampling. note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s r24 dac digital limiter control 1 8 limen 0 enable the dac digital limiter: 0=disabled 1=enabled 3:0 limboost 0000 limiter volume boost (can be used as a stand alone volume boost when limen=0): 0000=0db 0001=+1db 0010=+2db ? (1db steps) 1011=+11db 1100=+12db 1101 to 1111=reserved r25 dac digital limiter control 2 6:4 limlvl 000 programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1db 001=-2db 010=-3db 011=-4db 100=-5db 101 to 111=-6db table 28 dac digital limiter control
wm8974 production data w pd rev 4.2 march 2007 40 graphic equaliser a 5-band graphic eq is provided, which can be applied to the adc or dac path under control of the eqmode register bit. register address bit label default description r18 eq control 1 8 eqmode 1 0 = equaliser applied to adc path 1 = equaliser applied to dac path table 29 eq dac or adc path select the equaliser consists of low and high frequency shelving filters (band 1 and 5) and three peak filters for the centre bands. each has adjustable cut-off or centre frequency, and selectable boost (+/- 12db in 1db steps). the peak filters have selectable bandwidth. register address bit label default description 4:0 eq1g 01100 (0db) band 1 gain control. see table 35 for details. r18 eq band 1 control 6:5 eq1c 01 band 1 cut-off frequency: 00=80hz 01=105hz 10=135hz 11=175hz table 30 eq band 1 control register address bit label default description 4:0 eq2g 01100 (0db) band 2 gain control. see table 35 for details. 6:5 eq2c 01 band 2 centre frequency: 00=230hz 01=300hz 10=385hz 11=500hz r19 eq band 2 control 8 eq2bw 0 band 2 bandwidth control 0=narrow bandwidth 1=wide bandwidth table 31 eq band 2 control register address bit label default description 4:0 eq3g 01100 (0db) band 3 gain control. see table 35 for details. 6:5 eq3c 01 band 3 centre frequency: 00=650hz 01=850hz 10=1.1khz 11=1.4khz r20 eq band 3 control 8 eq3bw 0 band 3 bandwidth control 0=narrow bandwidth 1=wide bandwidth table 32 eq band 3 control
production data wm8974 w pd rev 4.2 march 2007 41 register address bit label default description 4:0 eq4g 01100 (0db) band 4 gain control. see table 35 for details 6:5 eq4c 01 band 4 centre frequency: 00=1.8khz 01=2.4khz 10=3.2khz 11=4.1khz r21 eq band 4 control 8 eq4bw 0 band 4 bandwidth control 0=narrow bandwidth 1=wide bandwidth table 33 eq band 4 control register address bit label default description 4:0 eq5g 01100 (0db) band 5 gain control. see table 35 for details. r22 eq band 5 gain control 6:5 eq5c 01 band 5 cut-off frequency: 00=5.3khz 01=6.9khz 10=9khz 11=11.7khz table 34 eq band 5 control gain register gain 00000 +12db 00001 +11db 00010 +10db ?. (1db steps) 01100 0db 01101 -1db 11000 -12db 11001 to 11111 reserved table 35 gain register table
wm8974 production data w pd rev 4.2 march 2007 42 analogue outputs the wm8974 has a single mono output and two outputs spkoutp and spoutn for driving a mono btl speaker. these analogue output stages are supplied from spkvdd and are capable of driving up to 1.5v rms signals (equivalent to 3v rms into a bridge tied speaker) as shown in figure 20. figure 20 speaker and mono analogue outputs the mono and speaker outputs have output driving stages which can be controlled by the register bits monoboost and spkboost respectively. each output st age has a selectable gain boost of 1.5x. when this boost is enabled the output dc level is also level shifted (from avdd/2 to 1.5xavdd/2) to prevent the signal from clipping. a dedicated amplifier, as shown in figure 20, is used to perform the dc level shift operation. this buffer must be enabled using the bufdcopen register bit for this operating mode. it should also be noted that if spkvdd is not equal to or greater than 1.5xavdd this boost mode may result in signals clipping. table 37 summarises the effect of the spkboost/monoboost control bits.
production data wm8974 w pd rev 4.2 march 2007 43 register address bit label defaul t description 2 spkboost 0 s peaker output boost stage control (see table 37 for details) 0=no boost (outputs are inverting buffers) 1 = 1.5x gain boost r49 output control 3 monoboost 0 mono output boost stage control (see table 37 for details) 0=no boost (output is inverting buffer) 1=1.5x gain boost r1 power management 1 8 bufdcopen 0 dedicated buffer for dc level shifting output stages when in 1.5x gain boost configuration. 0=buffer disabled 1=buffer enabled (required for 1.5x gain boost) table 36 output boost control spkboost/ monoboost output stage gain output dc level output stage configuration 0 1x avdd/2 inverting 1 1.5x 1.5xavdd/2 non-inverting table 37 output boost stage details spkoutp/spkoutn outputs the spkout pins can drive a single bridge tied 8 ? speaker or two headphone loads of 16 ? or 32 ? or a line output (see headphone output and line output sections, respectively). the signal to be output on skpkout comes from the s peaker mixer circuit and can be any combination of the dac output, the bypass path (output of the boost stage) and the aux input. the spkoutp/n volume is controlled by the spkvol register bits. note that gains over 0db may cause clipping if the signal is large. the spkmute register bit causes the s peaker outputs to be muted (the output dc level is driven out). the output pins remains at the same dc level (vmidop), so that no click noise is produced when muting or un-muting. the spkoutn pin always drives out an inverted version of the spkoutp si gnal. register address bit label default description 0 dac2spk 1 output of dac to s peaker mixer input 0 = not selected 1 = selected 1 byp2spk 0 bypass path (output of i nput boost stage) to speaker mixer input 0 = not selected 1 = selected r50 speaker mixer control 5 aux2spk 0 output of auxiliary amplifier to speaker mixer input 0 = not selected 1 = selected r40 bypass path attenuation control 1 spkattn 0 att enuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0db 1 = -10db table 38 speaker mixer control
wm8974 production data w pd rev 4.2 march 2007 44 register address bit label default description 7 spkzc 0 speaker volume control zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately 6 spkmute 0 speaker output mute enable 0=speaker output enabled 1=speaker output muted (vmidop) r54 speaker volume control 5:0 spkvol [5:0] 111001 (0db) speaker volume adjust 111111 = +6db 111110 = +5db ? (1.0 db steps) 111001=0db ? 000000=-57db table 39 spkout volume control zero cross timeout a zero-cross timeout function is also provided so that if zero cross is enabled on the input or output pgas the gain will automatically update after a timeout period if a zero cross has not occurred. this is enabled by setting slowclken. the timeout period is dependent on the clock input to the digital and is equal to 2 21 * input clock period. register address bit label default description r7 additional control 0 slowclken 0 slow clock enable. used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled table 40 timeout clock enable control mono mixer and output the monoout pin can drive a 16 ? or 32 ? headphone or a line output or be used as a dc reference for a headphone output (see headphone output section). it can be selected to drive out any combination of dac, bypass (output of input boost stage) and aux. this output is enabled by setting bit monoen.
production data wm8974 w pd rev 4.2 march 2007 45 register address bit label default description 0 dac2mono 0 output of dac to mono mixer input 0 = not selected 1 = selected 1 byp2mono 0 bypass path (output of i nput boost stage) to mono mixer input 0 = non selected 1 = selected 2 aux2mono 0 output of auxillary amplifier to mono mixer input: 0 = not selected 1 = selected r56 mono mixer control 6 monomute 0 0=no mute 1=output muted. during mute the mono output will output vmid which can be used as a dc reference for a headphone out. r40 bypass path attenuation control 2 monoattn 0 attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0db 1 = -10db table 41 mono mixer control enabling the outputs each analogue output of the wm8974 can be separately enabled or disabled. the analogue mixer associated with each output has a separate enable. all outputs are disabled by default. to save power, unused parts of the wm8974 should remain disabled. outputs can be enabled at any time, but it is not recommended to do so when bufio is disabled (bufioen=0), as this may cause pop noise (see ?power management? and ?applications information? sections). register address bit label default description 2 bufioen 0 unused input/output tie off buffer enable 8 bufdcopen 0 output stage 1.5xavdd/2 driver enable r1 power management 1 3 biasen 0 analogue amplifiers bias enable 2 spkmixen 0 s peaker mixer enable 3 monomixen 0 mono mixer enable 5 spkpen 0 spkoutp enable 6 spknen 0 spkoutn enable r3 power management 3 7 monoen 0 monoout enable note: all ?enable? bits are 1 = on, 0 = off table 42 output stages power management control unused analogue inputs/outputs whenever an analogue input/output is disabled, it remains connected to a voltage source (either avdd/2 or 1.5xavdd/2 as appropriate) through a resistor. this helps to prevent pop noise when the output is re-enabled. the resistance between the voltage buffer and the output pins can be controlled using the vroi contol bit. the default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. if a high impedance is desired for disabled outputs, vroi can then be set to 1, increasing the resistance to about 30k ? .
wm8974 production data w pd rev 4.2 march 2007 46 register address bit label default description r49 0 vroi 0 vref (avdd/2 or 1.5xavdd/2) to analogue output resistance 0: approx 1k ? 1: approx 30 k ? table 43 disabled outputs to vref resistance a dedicated buffer is available for tying off unused analogue i/o pins as shown in figure 21. this buffer can be enabled using the bufioen register bit. if the spkboost or monoboost bits are set then the relevant outputs will be tied to the output of the dc level shift buffer at 1.5xavdd/2 when disabled. table 44 summarises the tie-off options for the speaker and mono output pins. figure 21 unused input/output pin tie-off buffers monoen/ spkn/pen monoboost/ spkboost vroi output configuration 0 0 0 1k ? tieoff to avdd/2 0 0 1 30k ? tieoff to avdd/2 0 1 0 1k ? tieoff to 1.5xavdd/2 0 1 1 30k ? tieoff to 1.5xavdd/2 1 0 x output enabled (dc level=avdd/2) 1 1 x output enabled (dc level=1.5xavdd/2) table 44 unused output pin tie-off options
production data wm8974 w pd rev 4.2 march 2007 47 output switch when the device is configured with a 2-wire interface the csb/gpio pin can be used as a switch control input to automatically disable the speaker outputs and enable the mono output. for example when a line is plugged into a jack socket. in this mode, enabled by setting gpiosel=001, pin csb/gpio switches between mono and speaker outputs (e.g. when pin 12 is connected to a mechanical switch in the headphone socket to detect plug-in). the gpiopol bit reverses the polarity of the csb/gpio input pin. note that the speaker outputs and the mono output must be enabled for this function to work (see table 45). the csb/gpio pin has an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. this debounce circuit is clocked from a slow clock with period 2 21 x mclk, enabled using the slowclken register bit. gpiopol csb/gpio spknen/ spkpen monoen speaker enabled mono output enabled 0 0 x 0 no no 0 0 x 1 no yes 0 1 0 x no no 0 1 1 x yes no 1 0 x 0 no no 1 0 x 1 no yes 1 1 0 x no no 1 1 1 x yes no table 45 output switch operation (gpiosel=001) thermal shutdown the speaker outputs can drive very large currents. to protect the wm8974 from overheating a thermal shutdown circuit is included. the thermal shutdown can be configured to produce an interrupt when the device reaches approximately 125 o c. see general purpose input/output section. register address bit label default description r49 output control 1 tsden 1 thermal shutdown enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled table 46 thermal shutdown speaker output spkoutp/n can differentially drive a mono 8 ? bridge tied load (btl) speaker as shown below. figure 22 speaker output connection
wm8974 production data w pd rev 4.2 march 2007 48 headphone output the speaker outputs can drive a 16 ? or 32 ? headphone load, either through dc blocking capacitors, or dc coupled without any capacitor. headphone output using dc blocking capacitors: dc coupled headphone output: figure 23 recommended headphone output configurations when dc blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, f c . increasing the capacitance lowers f c , improving the bass response. smaller capacitance values will diminish the bass response. assuming a 16 ? load and c1, c2 = 220 f: f c = 1 / 2 r l c 1 = 1 / (2 x 16 ? x 220 f) = 45 hz in the dc coupled configuration, the headphone ?ground? is connected to the monoout pin. the monoout pin can be configured as a dc output driver by setting the monomute register bit. the dc voltage on monoout in this configuration is equal to the dc offset on the sproutp and spkoutn pins therefore no dc blocking capacitors are required. this saves space and material cost in portable applications. it is recommended to connect the dc coupled outputs only to headphones, and not to the line input of another device. although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded. mono output the mono output, can be used as a line output, a headphone output or as a psuedo ground for cap- less driving of loads by spkout. recomm ended external components are shown below. figure 24 recommended circuit for line output the dc blocking capacitors and the load resistance together determine the lower cut-off frequency, f c . assuming a 10 k ? load and c1 = 1 f: f c = 1 / 2 (r l +r 1 ) c 1 = 1 / (2 x 10.1k ? x 1 f) = 16 hz increasing the capacitance lowers f c , improving the bass response. smaller values of c1 will diminish the bass response. the function of r1 is to protect the line outputs from damage when used improperly.
production data wm8974 w pd rev 4.2 march 2007 49 digital audio interfaces the audio interface has four pins: ? adcdat: adc data output ? dacdat: dac data input ? frame: data alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk, and frame can be outputs when the wm8974 operates as a master, or inputs when it is a slave (see master and slave mode operation, below). four different audio data formats are supported: ? left justified ? right justified ? i 2 s ? dsp mode all of these modes are msb first. they are described in audio data formats, below. refer to the electrical characteristic section for timing information. master and slave mode operation the wm8974 audio interface may be configured as either master or slave. as a master interface device the wm8974 generates bclk and frame and thus controls sequencing of the data transfer on adcdat and dacdat. to set the device to master mode register bit ms should be set high. in slave mode (ms=0), the wm8974 responds with data to clocks it receives over the digital audio interfaces. audio data formats in left justified mode, the msb is available on the first rising edge of bclk following an frame transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each frame transition. figure 25 left justified audio interface (assuming n-bit word length) in right justified mode, the lsb is available on the last rising edge of bclk before a frame transition. all other bits are transmitted before (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each frame transition.
wm8974 production data w pd rev 4.2 march 2007 50 figure 26 right justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a frame transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 27 i 2 s audio interface (assuming n-bit word length) in dsp/pcm mode, the left channel msb is available on the 2 nd rising edge of bclk (selectable by lrp) following a rising edge of frame. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. framep should be set to 0 in this mode. figure 28 dsp/pcm mode audio interface
production data wm8974 w pd rev 4.2 march 2007 51 register address bit label default description 1 adclrswap 0 controls whether adc data appears in ?right? or ?left? phases of frame clock: 0=adc data appear in ?left? phase of frame 1=adc data appears in ?right? phase of frame 2 daclrswap 0 controls whether dac data appears in ?right? or ?left? phases of frame clock: 0=dac data appear in ?left? phase of frame 1=dac data appears in ?right? phase of frame 4:3 fmt 10 audio interface data format select: 00=right justified 01=left justified 10=i 2 s format 11= dsp/pcm mode 6:5 wl 10 word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) frame clock polarity 0=normal 1=inverted 7 framep 0 dsp mode control 1 = reserved 0 = configures interface so that msb is available on 2nd bclk rising edge after frame rising edge r4 audio interface control 8 bcp 0 bclk polarity 0=normal 1=inverted table 47 audio interface control audio interface control the register bits controlling audio format, word length and master / slave mode are summarised below. each audio interface can be controlled individually. register bit ms selects audio interface operation in master or slave mode. in master mode bclk, and frame are outputs. the frequency of bclk and frame in master mode are controlled with bclkdiv. these are divided down versions of master clock. this may result in short bclk pulses at the end of a frame if there is a non-integer ratio of bclks to frame clocks.
wm8974 production data w pd rev 4.2 march 2007 52 register address bit label default description 0 ms 0 sets the chip to be master over frame and bclk 0=bclk and frame clock are inputs 1=bclk and frame clock are outputs generated by the wm8974 (master) 4:2 bclkdiv 000 configures the bclk and frame output frequency, for use when the chip is master over bclk. 000=divide by 1 (bclk=mclk) 001=divide by 2 (bclk=mclk/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved 7:5 mclkdiv 010 sets the scaling for either the mclk or pll clock output (under control of cl ksel) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 r6 clock generation control 8 clksel 1 controls the source of the clock for all internal operation: 0=mclk 1=pll output table 48 clock control note that the setting mclkdiv=000 and bclkdiv=000 must not be used simultaneously. loopback setting the loopback register bit enables digital loopback. when this bit is set the output data from the adc audio interface is fed directly into the dac data input. companding the wm8974 supports a-law and -law companding on both transmit (adc) and receive (dac) sides. companding can be enabled on the dac or adc audio interfaces by writing the appropriate value to the dac_comp or adc_comp register bits respectively.
production data wm8974 w pd rev 4.2 march 2007 53 register address bit label default description 0 loopback 0 digital l oopback function 0=no loopback 1=loopback enabled, adc data output is fed directly into dac data input. 2:1 adc_comp 0 adc companding 00=off 01=reserved 10=-law 11=a-law r5 companding control 4:3 dac_comp 0 dac companding 00=off 01=reserved 10=-law 11=a-law table 49 companding control companding involves using a piecewise linear approximation of the following equations (as set out by itu-t g.711 standard) for data compression: -law (where =255 for the u.s. and japan): f(x) = ln( 1 + |x|) / ln( 1 + ) -1 x 1 a-law (where a=87.6 for europe): f(x) = a|x| / ( 1 + lna) } for x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) } for 1/a x 1 the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for a-law). the data will be transmitted as the first 8 msb?s of data. companding converts 13 bits ( -law) or 12 bits (a-law) to 8 bits using non-linear quantization. the input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. this is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. the companded signal is an 8- bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits). bit7 bit[6:4] bit[3:0] sign exponent mantissa table 50 8-bit companded word composition
wm8974 production data w pd rev 4.2 march 2007 54 u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 29 u-law companding a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 30 a-law companding audio sample rates the wm8974 sample rates for the adc and the dac are set using the sr register bits. the cutoffs for the digital filters and the alc attack/decay times stated are determined using these values and assume a 256fs master clock rate. if a sample rate that is not explicitly supported by the sr register settings is required then the closest sr value to that sample rate should be chosen, the filter characteristics and the alc attack, decay and hold times will scale appropriately.
production data wm8974 w pd rev 4.2 march 2007 55 register address bit label default description r7 additional control 3:1 sr 000 approximate sample rate (configures the coefficients for the internal digital filters): 000=48khz 001=32khz 010=24khz 011=16khz 100=12khz 101=8khz 110-111=reserved table 51 sample rate control master clock and phase locked loop (pll) the wm8974 has an on-chip phase-locked loop (pll) circuit that can be used to: generate master clocks for the wm8974 audio functions from another external clock, e.g. in telecoms applications. generate and output (on pin csb/gpio) a clock for another part of the system that is derived from an existing audio master clock. figure 31 shows the pll and internal clocking arrangment on the wm8974. the pll can be enabled or disabled by the pllen register bit. note: in order to minimise current consumption, the pll is disabled when the vmidsel[1:0] bits are set to 00b. vmidsel[1:0] must be set to a value other than 00b to enable the pll. register address bit label default description r1 power management 1 5 pllen 0 pll enable 0=pll off 1=pll on table 52 pllen control bit figure 31 pll and clock select circuit
wm8974 production data w pd rev 4.2 march 2007 56 the pll frequency ratio r = f 2 /f 1 (see figure 31) can be set using the register bits pllk and plln: plln = int r pllk = int (2 24 (r-plln)) example: mclk=12mhz, required clock = 12.288mhz. r should be chosen to ensure 5 < plln < 13. there is a fixed divide by 4 in the pll and a selectable divide by n after the pll which should be set to divide by 2 to meet this requirement. enabling the divide by 2 sets the required f 2 = 4 x 2 x 12.288mhz = 98.304mhz. r = 98.304 / 12 = 8.192 plln = int r = 8 k = int ( 2 24 x (8.192 ? 8)) = 3221225 = 3126e9h register address bit label default description 4 pllprescale 0 0 = mclk input not divided (default) 1= divide mclk by 2 before input to pll r36 pll n value 3:0 plln 1000 integer (n) part of pll input/output frequency ratio. use values greater than 5 and less than 13. r37 pll k value 1 5:0 pllk [23:18] 0ch r38 pll k value 2 8:0 pllk [17:9] 093h r39 pll k value 3 8:0 pllk [8:0] 0e9h fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). table 53 pll frequency ratio control the pll performs best when f 2 is around 90mhz. its stability peaks at n=8. some example settings are shown in table 54. mclk (mhz) (f1) desired output (mhz) f2 (mhz) prescale divide postscale divide r n (hex) k (hex) 12 11.2896 90.3168 1 2 7.5264 7 86c220 12 12.288 98.304 1 2 8.192 8 3126e8 13 11.2896 90.3168 1 2 6.947446 6 f28bd4 13 12.288 98.304 1 2 7.561846 7 8fd525 14.4 11.2896 90.3168 1 2 6.272 6 45a1ca 14.4 12.288 98.304 1 2 6.826667 6 d3a06e 19.2 11.2896 90.3168 2 2 9.408 9 6872af 19.2 12.288 98.304 2 2 10.24 a 3d70a3 19.68 11.2896 90.3168 2 2 9.178537 9 2db492 19.68 12.288 98.304 2 2 9.990243 9 fd809f 19.8 11.2896 90.3168 2 2 9.122909 9 1f76f7 19.8 12.288 98.304 2 2 9.929697 9 ee009e 24 11.2896 90.3168 2 2 7.5264 7 86c226 24 12.288 98.304 2 2 8.192 8 3126e8 26 11.2896 90.3168 2 2 6.947446 6 f28bd4 26 12.288 98.304 2 2 7.561846 7 8fd525 27 11.2896 90.3168 2 2 6.690133 6 boac93 27 12.288 98.304 2 2 7.281778 7 482296 table 54 pll frequency examples
production data wm8974 w pd rev 4.2 march 2007 57 general purpose input/output the csb/gpio pin can be configured to perform a variety of useful tasks by setting the gpiosel register bits. the gpio is only available in 2 wire mode. note that slowclken must be enabled when using the jack detect function. register address bit label default description 2:0 gpiosel 000 csb/gpio pin function select: 000=csb input 001= jack insert detect 010=temp ok 011=amute active 100=pll clk o/p 101=pll lock 110=reserved 111=reserved 3 gpiopol 0 gpio polarity invert 0=non inverted 1=inverted r8 gpio control 5:4 opclkdiv 00 pll output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 table 55 csb/gpio control control interface selection of control mode and 2-wire mode address the control interface can operate as either a 3-wire or 2-wire mpu interface. the mode pin determines the 2 or 3 wire mode as shown in table 56. the wm8974 is controlled by writing to registers through a serial control interface. a control word consists of 16 bits. the first 7 bits (b15 to b9) are address bits that select which control register is accessed. the remaining 9 bits (b8 to b0) are register bits, corresponding to the 9 bits in each control register. mode interface format low 2 wire high 3 wire table 56 control interface mode selection 3-wire serial control mode in 3-wire mode, every rising edge of sclk clocks in one data bit from the sdin pin. a rising edge on csb/gpio latches in a complete control word consisting of the last 16 bits. figure 32 3-wire serial control interface
wm8974 production data w pd rev 4.2 march 2007 58 2-wire serial control mode the wm8974 supports software control via a 2-wire serial bus. many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the wm8974). the wm8974 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the wm8974, then the wm8974 responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is ?1? when operating in write only mode, the wm8974 returns to the idle condition and wait for a new start condition and valid address. during a write, once the wm8974 has acknowledged a correct address, the controller sends the first byte of control data (b15 to b8, i.e. the wm8974 register address plus the first bit of register data). the wm8974 then acknowledges the first data byte by pulling sdin low for one clock pulse. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the wm8974 acknowledges again by pulling sdin low. transfers are complete when there is a low to high transition on sdin while sclk is high. after a complete sequence the wm8974 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device jumps to the idle condition. sdin sclk register address and 1st register data bit device address (7 bits) rd / wr bit ack (low) control byte 1 (bits 15 to 8) control byte 1 (bits 7 to 0) remaining 8 bits of register data stop start ack (low) ack (low) figure 33 2-wire serial control interface in 2-wire mode the wm8974 has a fixed device address, 0011010. resetting the chip the wm8974 can be reset by performing a write of any value to the software reset register (address 0 hex). this will cause all register values to be reset to their default values. in addition to this there is a power-on reset (por) circuit which ensures that the registers are set to default when the device is powered up. power supplies the wm8974 can use up to four separate power supplies: avdd and agnd: analogue supply, powers all analogue functions except the speaker output and mono output drivers. avdd can range from 2.5v to 3.6v and has the most significant impact on overall power consumption (except for power consumed in the headphone). a large avdd slightly improves audio quality. spkvdd and spkgnd: headphone and speaker supplies, power the speaker and mono output drivers. spkvdd can range from 2.5v to 5.5v. spkvdd can be tied to avdd, but it requires separate layout and decoupling capacitors to curb harmonic distortion. with a larger spkvdd, louder headphone and speaker outputs can be achieved with lower distortion. if spkvdd is lower than avdd (or 1.5 x avdd for boost mode), the output signal may be clipped. dcvdd: digital core supply, powers all digital functions except the audio and control interfaces. dcvdd can range from 1.71v to 3.6v, and has no effect on audio quality. the return path for dcvdd is dgnd, which is shared with dbvdd. dbvdd can range from 1.71v to 3.6v. dbvdd return path is through dgnd. it is possible to use the same supply voltage for all four supplies. however, digital and analogue supplies should be routed and decoupled separately on the pcb to keep digital switching noise out of the analogue signal paths.
production data wm8974 w pd rev 4.2 march 2007 59 note: ? dcvdd should be greater than or equal to 1.9v when using the pll. ? dcvdd is less than or equal to dbvdd recommended power up/down seqence in order to minimise output pop and click noise, it is recommended that the wm8974 device is powered up and down using one of the following sequences: power up when not using the output 1.5x boost stage: 1. turn on external power supplies. wait for supply voltage to settle. 2. set biasen = 1, bufioen = 1 and also the vmidsel[1:0] bits in the power management 1 register. * notes 1 and 2. 3. wait for the vmid supply to settle. * note 2. 4. enable dac by setting dacen = 1. 5. enable mixers as required. 6. enable output stages as required. power up when using the output 1.5x boost stage: 1. turn on external power supplies. wait for supply voltage to settle. 2. enable 1.5x output boost. set monoboost = 1 and spkboost = 1 as required. 3. set biasen = 1, bufioen = 1, bufdcopen = 1 and also the vmidsel[1:0] bits in the power management 1 register. * notes 1 and 2. 4. wait for the vmid supply to settle. * note 2. 5. enable dac by setting dacen = 1. 6. enable mixers as required. 7. enable output stages as required. power down (all cases): 1. soft mute dac by setting dacmu = 1. 2. disable power management register 1 by setting r1[8:0]=0x00. 3. disable all other output stages. 4. turn off external power supplies. notes: 1. this step enables the internal device bias buffer and the vmid buffer for unassigned inputs/outputs. this will provide a startup reference voltage for all inputs and outputs. this will cause the inputs and outputs to ramp towards vmid (not using output 1.5x boost) or 1.5 x (avdd/2) (using output 1.5x boost) in a way that is controlled and predictable (see note 2). 2. choose the value of the vmidsel bits based on the startup time (vmidsel=10 for slowest startup, vmidsel=11 for fastest startup). startup time is defined by the value of the vmidsel bits (the reference impedance) and the external decoupling capacitor on vmid. in addition to the power on sequence, it is recommended that the zero cross functions are used when changing the volume in the pgas to avoid any audible pops or clicks.
wm8974 production data w pd rev 4.2 march 2007 60 v pora dgnd internal por active device ready no power v por_off power supply por i 2 s clocks adc internal state t midrail_on analogue inputs adcdat pin gd adcen bit power down init normal operation normal operation init pd power down adc enabled adc enabled adc off t adcint dnc inppgaen bit t adcint inppga enabled dnc gd gd gd por por undefined vmid enabled vmidsel/ biasen bits avdd/2 t midrail_off (note 1) (note 2) (note 3) (note 4) v por_on figure 34 adc power up and down sequence (not to scale) symbol min typical max unit t midrail_on 500 ms t midrail_off >10 s t adcint 2/fs n /fs table 57 typical por operation (typical values, not tested)
production data wm8974 w pd rev 4.2 march 2007 61 notes: 1. the analogue input pin charge time, t midrail_on, is determined by the vmid pin charge time. this time is dependent upon the value of vmid decoupling capacitor and vmid pin input resistance and avdd power supply rise time. 2. the analogue input pin discharge time, t midrail_off, is determined by the analogue input coupling capacitor discharge time. the time, t midrail_off , is measured using a 1 f capacitor on the analogue input but will vary dependent upon the value of input coupling capacitor. 3. while the adc is enabled there will be lsb data bit activity on the adcdat pin due to system noise but no significant digital output will be present. 4. the vmidsel and bi asen bits must be set to enable analogue input midrail voltage and for normal adc operation. 5. adcdat data output delay from power up - with power supplies starting from 0v - is determined primarily by the vmid charge time. adc initialisation and power management bits may be set immediately after por is released; vmid charge time will be significantly longer and will dictate when the device is stabilised for analogue input. 6. adcdat data output delay at power up from device standby (power supplies already applied) is determined by adc initialisation time, 2/fs. figure 35 dac power up and down sequence (not to scale)
wm8974 production data w pd rev 4.2 march 2007 62 symbol min typical max unit t line_midrail_on 500 ms t line_midrail_off 1 s t hp_midrail_on 500 ms t hp__midrail_off 6 s t dacint 2/fs n /fs table 58 typical por operation (typical values, not tested) notes: 1. the lineout charge time, t line_midrail_on, is mainly determined by the vmid pin charge time. this time is dependent upon the value of vmid decoupling capacitor and vmid pin input resistance and avdd power supply rise time. the values above were measured using a 4.7 f capacitor. 2. it is not advisable to allow dacdat data input during initialisation of the dac. if the dac data value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue outputs. the same is also true if the dacdat is removed at a non-zero value, and no mute function has been applied to the signal beforehand. 3. the lineout discharge time, t line_midrail_off, is dependent upon the value of the lineout coupling capacitor and the leakage resistance path to ground. the values above were measured using a 10 f output capacitor. 4. the headphone charge time, t hp_midrail_on, is dependent upon the value of vmid decoupling capacitor and vmid pin input resistance and avdd power supply rise time. the values above were measured using a 4.7 f vmid decoupling capacitor. 5. the headphone discharge time, t hp_midrail_off, is dependent upon the value of the headphone coupling capacitor and the leakage resistance path to ground. the values above were measured using a 100 f capacitor. 6. the vmidsel and biasen bits must be set to enable analogue output midrail voltage and for normal dac operation.
production data wm8974 w pd rev 4.2 march 2007 63 power management saving power by reducing oversampling rate the default mode of operation of the adc and dac digital filters is in 64x oversampling mode. under the control of adcosr and dacosr the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. register address bit label default description r10 dac control 3 dacosr128 0 dac oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) r14 adc control 3 adcosr128 0 adc oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) table 59 adc and dac oversampling rate selection vmid the analogue circuitry will not work when vmid is disabled (vmidsel[1:0] = 00b). the impedance of the vmid resistor string, together with the decoupling capacitor on the vmid pin will determine the startup time of the vmid circuit. register address bit label default description r1 power management 1 1:0 vmidsel 00 reference string impedance to vmid pin (detemines startup time): 00=off (open circuit) 01=75k ? 10=300k ? 11=2.5k ? (for fastest startup) table 60 vmid impedance control biasen register address bit label default description r1 power management 1 3 biasen 0 analogue amplifier bias control 0=disabled 1=enabled table 61 biasen control estimated supply currents when either the dac or adc are enabled it is estimated that approximately 4ma will be drawn from dcvdd when dcvdd=1.8v and fs=48khz (this will be lower at lower sample rates). when the pll is enabled an additional 700 microamps will be drawn from dcvdd.
wm8974 production data w pd rev 4.2 march 2007 64 table 59 shows the estimated 3.3v avdd current drawn by various circuits, by register bit. register bit avdd current (milliamps) bufdcopen 0.1 monoen 0.2 pllen 1.4 (with clocks applied) micben 0.5 biasen 0.3 bufioen 0.1 vmidsel 10k=>0.3, less than 0.1 for 100k/500k boosten 0.2 inppgaen 0.2 adcen x64 (adcosr=0)=>2.6, x128 (adcosr=1)=>4.9 monoen 0.2 spkpen 1ma from spkvdd + 0.2ma from avdd in 5v m ode spknen 1ma from spkvdd + 0.2ma from avdd in 5v m ode monomixen 0.2 spkmixen 0.2 dacen x64 (dacosr=0)=>1.8, x128(dacosr=1)=>1.9 table 62 avdd supply current
production data wm8974 w pd rev 4.2 march 2007 65 register map addr b[15:9] def?t val dec hex register name b8 b7 b6 b5 b4 b3 b2 b1 b0 (hex) 0 00 software reset software reset 1 01 power manage?t 1 bufdcop en 0 auxen pllen micben biasen bufioen vmidsel 000 2 02 power manage?t 2 0 0 0 0 boosten 0 inppgaen 0 adcen 000 3 03 power manage?t 3 0 monoen spknen spkpen 0 mono mixen spk mixen 0 dacen 000 4 04 audio interface bcp framep wl fmt daclrsw ap adclrsw ap 0 050 5 05 companding ctrl 0 0 0 0 dac_comp adc_comp loopback 000 6 06 clock gen ctrl clksel mclkdiv bclkdiv 0 ms 140 7 07 additional ctrl 0 0 0 0 0 sr slowclke n 000 8 08 gpio 0 0 0 opclkdiv gpiopol gpiosel 000 10 0a dac control 0 0 dacmu deemph dacosr 128 amute 0 dacpol 000 11 0b dac digital vol 0 dacvol 0ff 14 0e adc control hpfen hpfapp hpfcut adcosr 128 0 0 adcpol 100 15 0f adc digital vol 0 adcvol 0ff 18 12 eq1 ? low shelf eqmode 0 eq1c eq1g 12c 19 13 eq2 ? peak 1 eq2bw 0 eq2c eq2g 02c 20 14 eq3 ? peak 2 eq3bw 0 eq3c eq3g 02c 21 15 eq4 ? peak 3 eq4bw 0 eq4c eq4g 02c 22 16 eq5 ? high shelf 0 0 eq5c eq5g 02c 24 18 dac limiter 1 limen limdcy limatk 032 25 19 dac limiter 2 0 0 limlvl limboost 000 27 1b notch filter 1 nfu nfen nfa0[13:7] 000 28 1c notch filter 2 nfu 0 nfa0[6:0] 000 29 1d notch filter 3 nfu 0 nfa1[13:7] 000 30 1e notch filter 4 nfu 0 nfa1[6:0] 000 32 20 alc control 1 alcsel 0 0 alcmax alcmin 038 33 21 alc control 2 alczc alchld alclvl 00b 34 22 alc control 3 alcmode alcdcy alcatk 032 35 23 noise gate 0 0 0 0 0 ngen ngth 000 36 24 pll n 0 0 0 0 pllpre scale plln[3:0] 008 37 25 pll k 1 0 0 0 pllk[23:18] 00c 38 26 pll k 2 pllk[17:9] 093 39 27 pll k 3 pllk[8:0] 0e9 40 28 attenuation ctrl 0 0 0 0 0 0 monoatt n spkattn 0 000 44 2c input ctrl mbvsel 0 0 0 0 auxmode aux2 inppga micn2 inppga micp2 inppga 003 45 2d inp pga gain ctrl 0 inppgazc inppga mute inppgavol 010 47 2f adc boost ctrl pgaboost 0 micp2boostvol 0 aux2boostvol 000 49 31 output ctrl 0 0 0 0 0 mono boost spk boost tsden vroi 002 50 32 spk mixer ctrl 0 0 0 aux2spk 0 0 0 byp2spk dac2spk 000
wm8974 production data w pd rev 4.2 march 2007 66 addr b[15:9] def?t val dec hex register name b8 b7 b6 b5 b4 b3 b2 b1 b0 (hex) 54 36 spk volume ctrl 0 spkzc spkmute spkvol 039 56 38 mono mixer ctrl 0 0 mono mute 0 0 0 aux2 mono byp2 mono dac2 mono 000 register bits by address notes: 1. default values of n/a indicate non-latched data bits (e.g. software reset or volume update bits). 2. register bits marked as "reserved" should not be changed from the default. register address bit label default description refer to 0 (00h) [8:0] r eset n/a software reset resetting the chip 8 bufdcopen 0 dedicated buffer for dc level shifting output stages when in 1.5x gain boost configuration. 0=buffer disabled 1=buffer enabled (required for 1.5x gain boost) analogue outputs 7 0 reserved 6 auxen 0 auxilliary input buffer enable 0 = off 1 = on auxiliary inputs 5 pllen 0 pll enable 0=pll off 1=pll on master clock and phase locked loop (pll) 4 micben 0 microphone bias enable 0 = off (high impedance output) 1 = on microphone biasing circuit 3 biasen 0 analogue amplifier bias control 0=disabled 1=enabled power management 2 bufioen 0 unused input/output tie off buffer enable 0=disabled 1=enabled enabling the outputs 1 (01h) 1:0 vmidsel 00 reference string impedance to vmid pin: 00=off (open circuit) 01=75k ? 10=300k ? 11=2.5k ? power management 8:5 0000 reserved 4 boosten 0 input boost enable 0 = boost stage off 1 = boost stage on input boost 3 0 reserved 2 inppgaen 0 input microphone pga enable 0 = disabled 1 = enabled input signal path 1 0 reserved 2 (02h) 0 adcen 0 adc enable control 0 = adc disabled 1 = adc enabled analogue to digital converter (adc) 3 (03h) 8 0 reserved
production data wm8974 w pd rev 4.2 march 2007 67 register address bit label default description refer to 7 monoen 0 monoout enable 0 = disabled 1 = enabled analogue outputs 6 spknen 0 spkoutn e nable 0 = disabled 1 = enabled analogue outputs 5 spkpen 0 spkoutp enable 0 = disabled 1 = enabled analogue outputs 4 0 reserved 3 monomixen 0 mono mixer enable 0 = disabled 1 = enabled analogue outputs 2 spkmixen 0 s peaker mixer enable 0 = disabled 1 = enabled analogue outputs 1 0 reserved 0 dacen 0 dac enable 0 = dac disabled 1 = dac enabled analogue outputs 8 bcp 0 bclk polarity 0=normal 1=inverted digital audio interfaces frame clock polarity 0=normal 1=inverted 7 framep 0 dsp mode control 1 = reserved 0 = configures the interface so that msb is available on 2nd bclk rising edge after frame rising edge digital audio interfaces 6:5 wl 10 word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits digital audio interfaces 4:3 fmt 10 audio interface data format select: 00=right justified 01=left justified 10=i 2 s format 11= dsp/pcm mode digital audio interfaces 2 daclrswap 0 controls whether dac data appears in ?right? or ?left? phases of frame clock: 0=dac data appear in ?left? phase of frame 1=dac data appears in ?right? phase of frame digital audio interfaces 1 adclrswap 0 controls whether adc data appears in ?right? or ?left? phases of frame clock: 0=adc data appear in ?left? phase of frame 1=adc data appears in ?right? phase of frame digital audio interfaces 4 (04h) 0 0 reserved 8:5 0000 reserved 5 (05h) 4:3 dac_comp 00 dac companding 00=off 01=reserved 10=-law 11=a-law digital audio interfaces
wm8974 production data w pd rev 4.2 march 2007 68 register address bit label default description refer to 2:1 adc_comp 00 adc companding 00=off 01=reserved 10=-law 11=a-law digital audio interfaces 0 loopback 0 digital loopback function 0=no loopback 1=loopback enabled, adc data output is fed directly into dac data input. digital audio interfaces 8 clksel 1 controls the source of the clock for all internal operation: 0=mclk 1=pll output digital audio interfaces 7:5 mclkdiv 010 sets the scaling for either the mclk or pll clock output (under control of clksel) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 digital audio interfaces 4:2 bclkdiv 000 configures the bclk and frame output frequency, for use when the chip is master over bclk. 000=divide by 1 (bclk=mclk) 001=divide by 2 (bclk=mclk/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved digital audio interfaces 1 0 reserved 6 (06h) 0 ms 0 sets the chip to be master over frame and bclk 0=bclk and frame clock are inputs 1=bclk and frame clock are outputs generated by the wm8974 (master) digital audio interfaces 8:4 00000 reserved 3:1 sr 000 approximate sample rate (configures the coefficients for the internal digital filters): 000=48khz 001=32khz 010=24khz 011=16khz 100=12khz 101=8khz 110-111=reserved audio sample rates 7 (07h) 0 0 reserved 8:6 000 reserved 8 (08h) 5:4 opclkdiv 00 pll output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 general purpose input output
production data wm8974 w pd rev 4.2 march 2007 69 register address bit label default description refer to 3 gpiopol 0 gpio polarity invert 0=non inverted 1=inverted general purpose input output 2:0 gpiosel 000 csb/gpio pin function select: 000=csb input 001= jack insert detect 010=temp ok 011=amute active 100=pll clk o/p 101=pll lock 110=reserved 111=reserved general purpose input output 9 (09h) 8:0 reserved 8:7 00 reserved 6 dacmu 0 dac soft mute enable 0 = dacmu disabled 1 = dacmu enabled output signal path 5:4 deemph 00 de-emphasis control 00 = no de-emphasis 01 = 32khz sample rate 10 = 44.1khz sample rate 11 = 48khz sample rate output signal path 3 dacosr128 0 dac oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) power management 2 amute 0 dac auto mute enable 0 = auto mute disabled 1 = auto mute enabled output signal path 1 0 reserved 10 (0ah) 0 dacpol 0 dac polarity invert 0 = no inversion 1 = dac output inverted output signal path 8 0 reserved 11 (0bh) 7:0 dacvol 11111111 dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db output signal path 12 (0ch) 8:0 reserved 13 (0dh) 8:0 reserved 8 hpfen 1 high pass filter enable 0=disabled 1=enabled analogue to digital converter (adc) 7 hpfapp 0 select audio mode or application mode 0=audio mode (1 st order, fc = ~3.7hz) 1=application mode (2 nd order, fc = hpfcut) analogue to digital converter (adc) 6:4 hpfcut 000 application mode cut-off frequency see table 11 for details. analogue to digital converter (adc) 3 adcosr128 0 adc oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) power management 14 (0eh) 2:1 00 reserved
wm8974 production data w pd rev 4.2 march 2007 70 register address bit label default description refer to 0 adcpol 0 adc polarity 0=normal 1=inverted analogue to digital converter (adc) 8 0 reserved 15 (0fh) 7:0 adcvol 11111111 adc digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db analogue to digital converter (adc) 16 (10h) 8:0 reserved 17 (11h) 8:0 reserved 8 eqmode 1 0 = equaliser applied to adc path 1 = equaliser applied to dac path output signal path 7 0 reserved 6:5 eq1c 01 eq band 1 cut-off frequency: 00=80hz 01=105hz 10=135hz 11=175hz output signal path 18 (12h) 4:0 eq1g 01100 eq band 1 gain control. see table 35 for details. output signal path 8 eq2bw 0 band 2 bandwidth control 0=narrow bandwidth 1=wide bandwidth output signal path 7 0 reserved 6:5 eq2c 01 band 2 centre frequency: 00=230hz 01=300hz 10=385hz 11=500hz output signal path 19 (13h) 4:0 eq2g 01100 band 2 gain control. see table 35 for details. output signal path 8 eq3bw 0 band 3 bandwidth control 0=narrow bandwidth 1=wide bandwidth output signal path 7 0 reserved 6:5 eq3c 01 band 3 centre frequency: 00=650hz 01=850hz 10=1.1khz 11=1.4khz output signal path 20 (14h) 4:0 eq3g 01100 band 3 gain control. see table 35 for details. output signal path 8 eq4bw 0 band 4 bandwidth control 0=narrow bandwidth 1=wide bandwidth output signal path 7 0 reserved 6:5 eq4c 01 band 4 centre frequency: 00=1.8khz 01=2.4khz 10=3.2khz 11=4.1khz output signal path 21 (15h) 4:0 eq4g 01100 band 4 gain control. see table 35 for details. output signal path 22 (16h) 8:7 00 reserved
production data wm8974 w pd rev 4.2 march 2007 71 register address bit label default description refer to 6:5 eq5c 01 band 5 cut-off frequency: 00=5.3khz 01=6.9khz 10=9khz 11=11.7khz output signal path 4:0 eq5g 01100 band 5 gain control. see table 35 for details. output signal path 8 limen 0 enable the dac digital limiter: 0=disabled 1=enabled output signal path 7:4 limdcy 0011 dac limiter decay time (per 6db gain change) for 44.1khz sampling. note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s output signal path 24 (18h) 3:0 limatk 0010 dac limiter attack time (per 6db gain change) for 44.1khz sampling. note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms output signal path 8:7 00 reserved 25 (19h) 6:4 limlvl 000 dac limiter programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1db 001=-2db 010=-3db 011=-4db 100=-5db 101 to 111=-6db output signal path
wm8974 production data w pd rev 4.2 march 2007 72 register address bit label default description refer to 3:0 limboost 0000 dac limiter volume boost (can be used as a stand alone volume boost when limen=0): 0000=0db 0001=+1db 0010=+2db ? (1db steps) 1011=+11db 1100=+12db 1101 to 1111=reserved output signal path 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. analogue to digital converter (adc) 7 nfen 0 notch filter enable: 0=disabled 1=enabled analogue to digital converter (adc) 27 (1bh) 6:0 nfa0[13:7] 0000000 notch filter a0 coefficient, bits [13:7] analogue to digital converter (adc) 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. analogue to digital converter (adc) 7 0 reserved 28 (1ch) 6:0 nfa0[6:0] 0000000 notch filter a0 coefficient, bits [6:0] analogue to digital converter (adc) 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. analogue to digital converter (adc) 7 0 reserved 29 (1dh) 6:0 nfa1[13:7] 0000000 notch filter a1 coefficient, bits [13:7] analogue to digital converter (adc) 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. analogue to digital converter (adc) 7 0 reserved 30 (1eh) 6:0 nfa1[6:0] 0000000 notch filter a1 coefficient, bits [6:0] analogue to digital converter (adc) 8 alcsel 0 alc function select: 0=alc off (pga gain set by inppgavol register bits) 1=alc on (alc controls pga gain) input limiter / automatic level control (alc) 7:6 reserved 5:3 alcmax 111 set maximum gain of pga when using alc: 111=+35.25db 110=+29.25db 101=+23.25db 100=+17.25db 011=+11.25db 010=+5.25db 001=-0.75db 000=-6.75db input limiter / automatic level control (alc) 32 (20h) 2:0 alcmin 000 set minimum gain of pga when using alc: 000=-12db 001=-6db 010=0db 011=+6db 100=+12db 101=+18db 110=+24db 111=+30db input limiter / automatic level control (alc)
production data wm8974 w pd rev 4.2 march 2007 73 register address bit label default description refer to 8 alczc 0 alc zero cross detection. 0 = disabled 1 = enabled input limiter / automatic level control (alc) 7:4 alchld 000 alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ? (time doubles with every step) 1111 = 43.691s input limiter / automatic level control (alc) 33 (21h) 3:0 alclvl 1011 alc target ? sets signal level at adc input 0000 = -28.5db fs 0001 = -27.0db fs ? (1.5db steps) 1110 = -7.5db fs 1111 = -6db fs input limiter / automatic level control (alc) 8 alcmode 0 determines the alc mode of operation: 0=alc mode 1=limiter mode. input limiter / automatic level control (alc) decay (gain ramp-up) time (alcmode =0) per step per 6db 90% of range 0000 410us 3.3ms 24ms 0001 820us 6.6ms 48ms 0010 1.64ms 13.1ms 192ms ? (time doubles with every step) 0011 1010 or higher 420ms 3.36s 24.576s decay (gain ramp-up) time (alcmode =1) per step per 6db 90% of range 0000 90.8us 726.4us 5.26ms 0001 181.6us 1.453ms 10.53ms 0010 363.2us 2.905ms 21.06ms ? (time doubles with every step) 34 (22h) 7:4 alcdcy 0011 1010 93ms 744ms 5.39s input limiter / automatic level control (alc) alc attack (gain ramp-down) time (alcmode = 0) per step per 6db 90% of range 0000 104us 832us 6ms 0001 208us 1.664ms 12ms 0010 416us 3.328ms 24.1ms ? (time doubles with every step) 0010 1010 or higher 106ms 852ms 6.18s alc attack (gain ramp-down) time (alcmode = 1) per step per 6db 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363.2us 2.62ms 0010 90.8us 726.4us 5.26ms ? (time doubles with every step) 3:0 alcatk 0010 1010 23.2ms 186ms 1.348s input limiter / automatic level control (alc) 8:4 00000 reserved 35 (23h) 3 ngen 0 alc noise gate function enable 1 = enable 0 = disable input limiter / automatic level control (alc)
wm8974 production data w pd rev 4.2 march 2007 74 register address bit label default description refer to 2:0 ngth 000 alc noise gate threshold: 000=-39db 001=-45db 010=-51db ? (6db steps) 111=-81db input limiter / automatic level control (alc) 8:5 0000 reserved 4 pllprescale 0 0 = mclk input not divided (default) 1 = divide mclk by 2 before input pll master clock and phase locked loop (pll) 36 (24h) 3:0 plln[3:0] 1000 integer (n) part of pll input/output frequency ratio. use values greater than 5 and less than 13. master clock and phase locked loop (pll) 8:6 000 reserved 37 (25h) 5:0 pllk[23:18] 001100 fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). master clock and phase locked loop (pll) 38 (26h) 8:0 pllk[17:9] 010010011 fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). master clock and phase locked loop (pll) 39 (27h) 8:0 pllk[8:0] 011101001 fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). master clock and phase locked loop (pll) 8:3 000000 reserved 2 monoattn 0 attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0db 1 = -10db analogue outputs 1 spkattn 0 att enuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0db 1 = -10db analogue outputs 40 (28h) 0 0 reserved 8 mbvsel 0 microphone bias voltage control 0 = 0.9 * avdd 1 = 0.65 * avdd input signal path 7:4 0000 reserved 3 auxmode 0 auxiliary input mode 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed) input signal path 2 aux2inppga 0 select aux amplifier output as input pga signal source. 0=aux not connected to input pga 1=aux connected to input pga amplifier negative terminal. input signal path 1 micn2inppga 1 connect micn to input pga negative terminal. 0=micn not connected to input pga 1=micn connected to input pga amplifier negative terminal. input signal path 44 (2ch) 0 micp2inppga 1 connect input pga amplifier positive terminal to micp or vmid. 0 = input pga amplifier positive terminal connected to vmid 1 = input pga amplifier positive terminal connected to micp through variable resistor string input signal path 8 0 reserved 45 (2dh) 7 inppgazc 0 input pga zero cross enable: 0=update gain when gain register changes 1=update gain on 1 st zero cross after gain register write. input signal path
production data wm8974 w pd rev 4.2 march 2007 75 register address bit label default description refer to 6 inppgamute 0 mute control for input pga: 0=input pga not muted, normal operation 1=input pga muted (and disconnected from the following input boost stage). input signal path 5:0 inppgavol 010000 input pga volume 000000 = -12db 000001 = -11.25db . 010000 = 0db . 111111 = 35.25db input signal path 8 pgaboost 0 input boost 0 = pga output has +0db gain through input boost stage. 1 = pga output has +20db gain through input boost stage. input signal path 7 0 reserved 6:4 micp2boostvo l 000 controls the micp pin to the input boost stage (nb, when using this path set micp2inppga=0): 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage input signal path 3 0 reserved 47 (2fh) 2:0 aux2boostvol 000 controls the auxilliary amplifier to the input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage input signal path 8:4 00000 reserved 3 monoboost 0 mono output boost stage control (see table 37 for details) 0=no boost (output is inverting buffer) 1=1.5x gain boost analogue outputs 2 spkboost 0 s peaker output boost stage control (see table 37 for details) 0=no boost (outputs are inverting buffers) 1 = 1.5x gain boost analogue outputs 1 tsden 1 thermal shutdown enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled output switch 49 (31h) 0 vroi 0 vref (avdd/2 or 1.5xavdd/2) to analogue output resistance 0: approx 1k ? 1: approx 30 k ? analogue outputs 8:6 000 reserved 5 aux2spk 0 output of auxiliary amplifier to s peaker mixer input 0 = not selected 1 = selected analogue outputs 4:2 000 reserved 1 byp2spk 0 bypass path (output of i nput boost stage) to speaker mixer input 0 = not selected 1 = selected analogue outputs 50 (32h) 0 dac2spk 0 output of dac to speaker mixer input 0 = not selected 1 = selected analogue outputs
wm8974 production data w pd rev 4.2 march 2007 76 register address bit label default description refer to 8 7 spkzc 0 s peaker volume control zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately analogue outputs 6 spkmute 0 s peaker output mute enable 0=speaker output enabled 1=speaker output muted (vmidop) analogue outputs 54 (36h) 5:0 spkvol 111001 speaker volume adjust 111111 = +6db 111110 = +5db ? (1.0 db steps) 111001=0db ? 000000=-57db analogue outputs 8:7 0 reserved 6 monomute 0 monoout mute control 0=no mute 1=output muted. during mute the mono output will output vmid which can be used as a dc reference for a headphone out. analogue outputs 5:3 0 reserved 2 aux2mono 0 output of auxilliary amplifier to mono mixer input: 0 = not selected 1 = selected analogue outputs 1 byp2mono 0 bypass path (output of i nput boost stage) to mono mixer input 0 = non selected 1 = selected analogue outputs 56 (38h) 0 dac2mono 0 output of dac to mono mixer input 0 = not selected 1 = selected analogue outputs
production data wm8974 w pd rev 4.2 march 2007 77 digital filter characteristics parameter test conditions min typ max unit adc filter +/- 0.025db 0 0.454fs passband -6db 0.5fs passband ripple +/- 0.025 db stopband 0.546fs stopband attenuation f > 0.546fs -60 db group delay 21/fs adc high pass filter -3db 3.7 -0.5db 10.4 high pass filter corner frequency -0.1db 21.6 hz dac filter +/- 0.035db 0 0.454fs passband -6db 0.5fs passband ripple +/-0.035 db stopband 0.546fs stopband attenuation f > 0.546fs -80 db group delay 29/fs table 63 digital filter characteristics terminology 1. stop band attenuation (db) ? the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of the frequency response in the pass-band region 3. note that this delay applies only to the filters and does not include additional delays through other digital circuits. see table 64 for the total delay. parameter test conditions min typ max unit adc path group delay eq disabled 26/fs 28/fs 30/fs total delay (adc analogue input to digital audio interface output) eq enabled 27/fs 29/fs 31/fs dac path group delay eq disabled 34/fs 36/fs 38/fs total delay (audio interface input to dac analogue output) eq enabled 35/fs 37/fs 39/fs table 64 total group delay notes: 1. wind noise filter is disabled.
wm8974 production data w pd rev 4.2 march 2007 78 dac filter responses -120 -100 -80 -60 -40 -20 0 00.511.522.53 frequency (fs) response (db) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.1 0.2 0.3 0.4 0.5 frequency (fs) response (db) figure 36 dac digital filter frequency response figure 37 dac digital filter ripple adc filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 frequency (fs) response (db) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.1 0.2 0.3 0.4 0.5 frequency (fs) response (db) figure 38 adc digital filter frequency response figure 39 adc digital filter ripple
production data wm8974 w pd rev 4.2 march 2007 79 de-emphasis filter responses -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 2000 4000 6000 8000 10000 12000 14000 16000 frequency (hz) response (db) -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 2000 4000 6000 8000 10000 12000 14000 16000 frequency (hz) response (db) figure 40 de-emphasis frequency response (32khz) figure 41 de-emphasis error (32khz) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 frequency (hz) response (db) -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0 5000 10000 15000 20000 frequency (hz) response (db) figure 42 de-emphasis frequency response (44.1khz) figure 43 de-emphasis error (44.1khz) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 frequency (hz) response (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 5000 10000 15000 20000 frequency (hz) response (db) figure 44 de-emphasis frequency response (48khz) figure 45 de-emphasis error (48khz)
wm8974 production data w pd rev 4.2 march 2007 80 highpass filter the wm8974 has a selectable digital highpass filter in the adc filter path. this filter has two modes, audio and applications. in audio mode the filter is a 1 st order iir with a cutoff of around 3.7hz. in applications mode the filter is a 2 nd order high pass filter with a selectable cutoff frequency. -40 -35 -30 -25 -20 -15 -10 -5 0 5 0 5 10 15 20 25 30 35 40 45 frequency (hz) response (db) -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) figure 46 adc highpass filter response, hpfapp=0 figure 47 adc highpass filter responses (48khz), hpfapp=1, all cutoff settings shown. -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) figure 48 adc highpass filter responses (24khz), hpfapp=1, all cutoff settings shown. figure 49 adc highpass filter responses (12khz), hpfapp=1, all cutoff settings shown.
production data wm8974 w pd rev 4.2 march 2007 81 5-band equaliser the wm8974 has a 5-band equaliser which can be applied to either the adc path or the dac path. the plots from figure 50 to figure 63 show the frequency responses of each filter with a sampling frequency of 48khz, firstly showing the different cut-off/centre frequencies with a gain of 12db, and secondly a sweep of the gain from -12db to +12db for the lowest cut-off/centre frequency of each filter. 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 50 eq band 1 ? low frequency shelf filter cut-offs figure 51 eq band 1 ? gains for lowest cut-off frequency 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 52 eq band 2 ? peak filter centre frequencies, eq2bw=0 figure 53 eq band 2 ? peak filter gains for lowest cut-off frequency, eq2bw=0 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 54 eq band 2 ? eq2bw=0, eq2bw=1
wm8974 production data w pd rev 4.2 march 2007 82 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 55 eq band 3 ? peak filter centre frequencies, eq3bw=0 figure 56 eq band 3 ? peak filter gains for lowest cut-off frequency, eq3bw=0 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 57 eq band 3 ? eq3bw=0, eq3bw=1
production data wm8974 w pd rev 4.2 march 2007 83 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 58 eq band 4 ? peak filter centre frequencies, eq3bw=0 figure 59 eq band 4 ? peak filter gains for lowest cut-off frequency, eq4bw=0 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 60 eq band 4 ? eq3bw=0, eq3bw=1 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 61 eq band 5 ? high frequency shelf filter cut-offsfigure 62 eq band 5 ? gains for lowest cut-off frequency
wm8974 production data w pd rev 4.2 march 2007 84 figure 63 shows the result of having the gain set on more than one channel simultaneously. the blue traces show each band (lowest cut-off/centre frequency) with 12db gain. the red traces show the cumulative effect of all bands with +12db gain and all bands -12db gain, with eqxbw=0 for the peak filters. 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 20 frequency (hz) magnitude (db) figure 63 cumulative frequency boost/cut
production data wm8974 w pd rev 4.2 march 2007 85 applications information recommended external components figure 64 recommended external components
wm8974 production data w pd rev 4.2 march 2007 86 package diagram dm045.a fl: 24 pin qfn plastic package 4 x 4 x 0.9 mm body, 0.50 mm lead pitch index area (d/2 x e/2) top view d e 4 notes: 1. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 2. falls within jedec, mo-220, variation vggd-2. 3. all dimensions are in millimetres. 4. the terminal #1 identifier and terminal numbering convention shall conform to jedec 95-1 spp-002. 5. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. refer to applications note wan_0118 for further information regarding pcb footprints and qfn package soldering. 7. depending on the method of lead termination at the edge of the package, pull back (l1) may be present. 8. this drawing is subject to change without notice. a3 g t h w b exposed lead half etch tie bar dimensions (mm) symbols min nom max note a a1 a3 0.80 0.90 1.00 0.05 0.02 0 0.20 ref b d d2 e e2 e l 0.30 0.18 4.00 2.80 2.70 2.55 0.50 bsc 0.30 0.40 0.50 2 2 4.00 2.80 2.70 2.55 0.10 aaa bbb ccc ref: 0.15 0.10 jedec, mo-220, variation vggd-2. tolerances of form and position 0.25 h 0.1 0.213 g t 0.1 w 0.2 detail 1 detail 2 a 6 1 13 18 24 19 12 e d2 b 7 1 b c bbb m a bottom view c aaa 2 x c aaa 2 x 1 c a3 seating plane detail 2 a1 c 0.08 c ccc a 5 side view l l1 l1 0.15 0.03 7 exposed ground paddle 6 detail 1 0.32mm 45 degrees exposed ground paddle e datum detail 2 terminal tip e/2 1 r e2 see detail 2
production data wm8974 w pd rev 4.2 march 2007 87 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance pl aced thereon by any person. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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